Celebrity Inventors
Penn Jillette of Penn and Teller fame has patented a "Hydro-Therapeutic Stimulator", which uses a hot tub for stimulation.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8189378 | Reducing program disturb in non-volatile storage A non-volatile semiconductor storage system is programmed in a manner that reduces program disturb by applying a higher boosting voltage on one or more word lines that are connected to non-volatile storage elements that may be partially programmed. ... | 05/29/2012 |
| 8189379 | Reduction of read disturb errors in NAND FLASH memory Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system utilizing modified or extra FLASH memory cells. ... | 05/29/2012 |
| 8184479 | Reducing the impact of interference during programming A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, ... | 05/22/2012 |
| 8184478 | Apparatus with reduced program disturb in non-volatile storage A non-volatile semiconductor storage system is programmed in a manner that reduces program disturb by applying a higher boosting voltage on one or more word lines that are connected to non-volatile storage elements that may be partially programmed. ... | 05/22/2012 |
| 8179717 | Maintaining integrity of preloaded content in non-volatile memory during surface mounting A non-volatile memory chip package is prepared for surface mounting to a substrate in a solder reflow process by programming erased blocks to higher threshold voltage levels, to improve data retention for blocks which are preloaded with content, such as by an electr... | 05/15/2012 |
| 8174881 | Techniques for reducing disturbance in a semiconductor device Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plu... | 05/08/2012 |
| 8174882 | Method of programming a non-volatile memory device for enhancing a channel boosting of a bit line inhibited from programming A method of programming a non-volatile memory device includes applying a first pass voltage to word lines in a direction of a source select line based on a first word line selected for a program operation, wherein the word lines do not include a second word line adj... | 05/08/2012 |
| 8169822 | Data state-dependent channel boosting to reduce channel-to-floating gate coupling in memory In a programming operation, selected storage elements on a selected word line are programmed while unselected storage elements on the selected word line are inhibited from programming by channel boosting. To provide a sufficient but not excessive level of boosting, ... | 05/01/2012 |
| 8164950 | Reduction of punch-through disturb during programming of a memory device A punch-through disturb effect in a memory device can be reduced by biasing a selected word line at a program voltage to program a selected memory cell, biasing word lines on the drain side of the series string with a Vpass voltage, turning off an adjacen... | 04/24/2012 |
| 8164951 | Method and apparatus for providing a non-volatile memory with reduced cell capacitive coupling A flash memory architecture that provides a mechanism for reducing floating gate to floating gate coupling. The floating gates of the memory cells are shifted, either vertically or horizontally thereby offsetting the floating gates of the memory cells to an interven... | 04/24/2012 |
| 8159874 | Cell operation monitoring Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of indiv... | 04/17/2012 |
| 8154919 | Method of reading nonvolatile memory device and nonvolatile memory device for implementing the method A nonvolatile memory device includes a read margin critical value calculation unit configured to calculate a critical value of a read margin between a read voltage and a threshold voltage of a specific cell, an interference value calculation unit configured to calcu... | 04/10/2012 |
| 8154918 | Method for page- and block based scrambling in non-volatile memory A method and system for programming and reading data with reduced read errors in a memory device. In one approach, date to be written to the memory device is scrambled using a first pseudo random number which is generated based on a page of the memory device to whic... | 04/10/2012 |
| 8139406 | Non-volatile memory system and programming method of the same A programming method for a non-volatile memory system includes storing multi-page program data and buffering the multi-page program data from a page buffer to a memory block and programming the multi-page program data through a predetermined number of program operat... | 03/20/2012 |
| 8139407 | Nonvolatile semiconductor memory device including NAND-type flash memory and the like A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory... | 03/20/2012 |
| 8130542 | Reading non-volatile multilevel memory cells Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile multilevel memory cells. One method includes receiving a request to read data stored in a first cell of a first word line, performing a read operation on an... | 03/06/2012 |
| 8125825 | Memory system protected from errors due to read disturbance and reading method thereof A method of reading a memory system including a flash memory includes: reading data from a page in a first block of the flash memory, incrementing a counter each time data is read from the page to store a corresponding number of read-out cycles of the flash memory, ... | 02/28/2012 |
| 8120952 | Memory device with a decreasing dynamic pass voltage for reducing read-disturb effect The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying sensing voltages to selected access lines for sensing selected memory cells. The method also includes applying a dynamic pass v... | 02/21/2012 |
| 8107286 | Three-dimensional nonvolatile semiconductor memory device for curbing a leak current and method of data read therein A nonvolatile semiconductor memory device comprises: a memory cell array having a plurality of memory strings each having a plurality of memory cells connected in series; and a control circuit configured to execute a read operation for reading data from the memory c... | 01/31/2012 |
| 8102704 | Method of preventing coupling noises for a non-volatile semiconductor memory device Disclosed is a method of preventing coupling noises for a non-volatile semiconductor memory device. According to the method, if an edge of a write operation signal overlaps an activated period of a read operation signal a check result is generated. The write operati... | 01/24/2012 |
| 8094492 | Reducing the impact of interference during programming A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, ... | 01/10/2012 |
| 8089804 | Non-volatile semiconductor memory device using weak cells as reading identifier A non-volatile semiconductor memory is configured to monitor for onset of a read disturbance (e.g., due to soft programming) and to carry out operations to protect data therein. A non-volatile semiconductor memory has a memory cell array that includes normal memory ... | 01/03/2012 |
| 8064250 | Providing a ready-busy signal from a non-volatile memory device to a memory controller A common standard may be used for both dynamic random access memories and non-volatile memories, despite the fact that the non-volatile memory generally needs bidirectional communications to coordinate writing with a memory controller. In one embodiment, a package c... | 11/22/2011 |
| 8064251 | Memory device and method having charge level assignments selected to minimize signal coupling A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the cells in a row using a set of bit state assignments chosen by evaluating data that are to be written to the ... | 11/22/2011 |
| 8059455 | Partial scrambling to reduce correlation Decorrelation is provided between data stored in respective pairs of adjacent memory cells in a plurality of bit lines of a flash memory. Each of the pairs of adjacent memory cells is located along a respective one of the bitlines and common to two adjacent wordline... | 11/15/2011 |
| 8054681 | Read, verify word line reference voltage to track source level A non-volatile memory device has individual pages of memory cells to be sensed in parallel. The memory device includes a source level tracking circuit coupled to receive a predetermined word line voltage from a word line voltage supply and the voltage level at the a... | 11/08/2011 |
| 8050086 | Distortion estimation and cancellation in memory devices A method for operating a memory (28) includes storing data in a group of analog memory cells (32) of the memory as respective first voltage levels. After storing the data, second voltage levels are read from the respective analog memory cells. The seco... | 11/01/2011 |
| 8045372 | Flash memory device and method of operating the same A flash memory device includes a plurality of memory cell blocks, an operating voltage generator, a block switching unit and a voltage supply circuit. Each of the plurality of memory cell blocks includes select lines and word lines, and has pass word lines included ... | 10/25/2011 |
| 8045374 | Erase verification method of flash memory by selectively assigning deselected sectors A suitable erase verification (ERSV) method of a flash memory apparatus is provided, which is different from the conventional ERSV method. That is, by managing the ERSV operation on the flash memory after at least once of erase operation, a flash memory controller i... | 10/25/2011 |
| 8045373 | Method and apparatus for programming memory cell array Disclosed are a method and device for programming an array of memory cells. ... | 10/25/2011 |
| 8036028 | Method of programming a non-volatile memory device with timely-adjusted voltages applied to word lines to prevent program disturb A method of programming a non-volatile memory device with timely-adjusted voltages applied to word lines to prevent program disturb includes applying a first pass voltage to word lines in a direction of a source select line based on a first word line selected for a ... | 10/11/2011 |
| 8031521 | Reprogramming non-volatile memory devices for read disturbance mitigation The present disclosure includes systems and techniques relating to non-volatile memory. The systems and techniques can include accessing a threshold value that is associated with a data area of a non-volatile memory structure, performing a comparison using the thres... | 10/04/2011 |
| 8031520 | Method for reading and programming a charge-trap memory device compensated for an array/second-bit/neighbor-bit effect A method for programming a memory is provided. The memory includes a number of cells and has a preset PV level for a target cell. The method includes programming a first-side of the target cell to have a Vt level not lower than the preset PV level; reading a Vt leve... | 10/04/2011 |
| 8027193 | Semiconductor memory device having bit line disturbance preventing unit A read data path circuit for use in the semiconductor memory device includes a bit line sense amplifier, a local input/output line sense amplifier, a column selection unit operationally coupling a bit line pair with the local input/output line pair in response to a ... | 09/27/2011 |
| 8023322 | Non-volatile memory and method with reduced neighboring field errors A memory device and a method thereof allow programming and sensing a plurality of memory cells in parallel in order to minimize errors caused by coupling from fields of neighboring cells and to improve performance. The memory device and method have the plurality of ... | 09/20/2011 |
| 8023321 | Flash memory program inhibit scheme A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme... | 09/20/2011 |
| 8018766 | Concurrent intersymbol interference encoding in a solid state memory Methods and devices are provided for concurrent intersymbol interference encoding in a solid state memory. In an illustrative embodiment, a write data signal is received as input to a processing component. A channel-effect-corrected encoding of the write data signal... | 09/13/2011 |
| 8004885 | Three-dimensional memory device and driving method thereof A driving method of a three-dimensional memory device having a plurality of layers is provided. One of the layers is selected. A well of the selected layer is biased with a first well voltage. A word line voltage is applied to a selected word line of the selected la... | 08/23/2011 |
| 7995387 | System and method to read data subject to a disturb condition Systems and methods for reading data are disclosed. In a particular embodiment, a method includes measuring characteristics of a plurality of cells at a memory. The characteristics correspond to a plurality of values including a first value stored at a particular ce... | 08/09/2011 |
| 7995385 | Memory array of pairs of nonvolatile memory cells using Fowler-Nordheim programming and erasing A system comprising a program component that programs one or more non-volatile memory (“NVM”) cells of an array of pairs of NVM cells using FN tunneling, an erase component that erases the one or more NVM cells of the array of pairs of NVM cells using FN tunneli... | 08/09/2011 |
