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Cloaking System Using Optoelectronically Controlled Camouflage
A Cloaking System designed to operate in the visible light spectrum, utilizes optoelectronics and/or photonic components to conceal an object within it.
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| Number | Title | Issue Date |
| 7032039 | Method for identification of SPI compatible serial memory devices A method for identifying Serial Peripheral Interface (SPI) compatible serial interface memory devices. A microprocessor sends a single command requesting identification information to an SPI device installed on the SPI bus. A byte string, including the JEDEC manufac... | 04/18/2006 |
| 7031196 | Nonvolatile semiconductor memory and operating method of the memory A method of programming the memory cell comprises setting the memory cell to an initial state of a first gate threshold voltage, performing a processing sequence including: applying a voltage bias between the gate and the first junction region to cause electric hole... | 04/18/2006 |
| 7031192 | Non-volatile semiconductor memory and driving method A data control unit is used to proved program, erase and verify signals to a non-volatile metal-oxide3-nitride-oxide-semiconductor (MONOS) memory. The data control unit comprises a plurality of sub-units that each contains a sense amplifier, two bi-directional flip-... | 04/18/2006 |
| 7031191 | Stabilization method for drain voltage in non-volatile multi-level memory cells and related memory device A method and an electronic device for stabilizing the voltage on the drain terminals of multi-level non-volatile memory cells during programming thereof. The voltage is provided by a drain voltage regulator having an output connected to the drain terminals at a comm... | 04/18/2006 |
| 7027329 | Nonvolatile semiconductor memory and programming method for the same A semiconductor memory has a memory cell matrix including a plurality of first and second cell columns alternately arranged along a row-direction, each of cell columns is implemented by a plurality of memory cell transistors, and peripheral circuits configured to dr... | 04/11/2006 |
| 7027328 | Integrated circuit memory device and method Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the ch... | 04/11/2006 |
| 7023729 | Microcomputer and microprocessor having flash memory operable from single external power supply A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations. The microcomputer comprises a voltage clamp unit ... | 04/04/2006 |
| 7023728 | Semiconductor memory system including selection transistors A semiconductor memory system comprising a memory matrix including a plurality of memory cells arranged in rows and columns and connected to a plurality of column lines, each memory cell of the same column having a first and a second terminal connected to a first an... | 04/04/2006 |
| 7020020 | Low voltage non-volatile memory cells using twin bit line current sensing A non-volatile memory cell operating at low voltage by means of impact ionization for programming. Impact ionization arises from a charge injector, such as a diode, created in the substrate of a floating gate charge storage transistor. The charge supply is biased by... | 03/28/2006 |
| 7020007 | Non-volatile static random access memory Non-volatile SRAMs having an improved recall characteristic are disclosed. An illustrated non-volatile SRAM includes a plurality of unit memory cells arranged in an array. Each of the plurality of unit memory cells comprises a SRAM unit and a non-volatile circuit. T... | 03/28/2006 |
| 7016225 | Four-bit non-volatile memory transistor and array A non-volatile memory cell capable of storing more than two bits of information. The NVM cell includes a semiconductor region having a first conductivity type, and a plurality of field isolation regions located in the semiconductor region. Four or more source/drain ... | 03/21/2006 |
| 7016219 | Single transistor non-volatile memory system, design, and operation Described are area-efficient non-volatile memory systems. Non-volatile memory cells in these systems include only one transistor, two fewer than conventional non-volatile memory cells, and reduced interconnect. The simplicity of the memory cells reduces memory-syste... | 03/21/2006 |
| 7015538 | Non-volatile memory and method for manufacturing non-volatile memory A coupling oxide film is formed on a silicon substrate, a polysilicon film is further formed thereupon, and a low-temperature oxide film is deposited to a thickness of 10 nm, for example. Next, a silicon nitride film is formed on this low-temperature oxide film, and... | 03/21/2006 |
| 7015080 | Manufacturing method of semiconductor device The present invention makes it is possible to provide a manufacturing method of a semiconductor device by which damage by plasma process or doping process during a LDD formation process can be reduced as much as possible. Charge density to be stored in a gate electr... | 03/21/2006 |
| 7012835 | Flash memory data correction and scrub techniques In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid da... | 03/14/2006 |
| 7012297 | Scalable flash/NV structures and devices with extended endurance Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of the gate stack includes a tunnel medium, a high K charge blocking and charge storing medium, and an inject... | 03/14/2006 |
| 7012295 | Semiconductor memory with peripheral transistors having gate insulator thickness being thinner than thickness of memory and select transistors The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-elect... | 03/14/2006 |
| 7007131 | Method and apparatus including special programming mode circuitry which disables internal program verification operations by a memory A method wherein a special programming mode of a memory is entered and internal program verification by the memory is disabled. An apparatus is also described having a host processor and a memory with special programming mode circuitry. The memory includes automatio... | 02/28/2006 |
| 7006376 | Tunable cantilever apparatus and method for making same Mass distribution within programmable surface control devices is controlled growing or dissolving an electrodeposition of metal and/or metal ions from a solid solution upon application of a suitable electric field. One such programmable surface control device includ... | 02/28/2006 |
| 7005344 | Method of forming a device with a gallium nitride or gallium aluminum nitride gate A floating gate transistor has a reduced barrier energy at an interface between a gallium nitride (GaN) or gallium aluminum nitride (GaAlN) floating gate an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is... | 02/28/2006 |
| 7005338 | Nonvolatile memory cell with a floating gate at least partially located in a trench in a semiconductor substrate A floating gate (110) of a nonvolatile memory cell is formed in a trench (114) in a semiconductor substrate (220). A dielectric (128) covers the surface of the trench. The wordline (140) has a portion overlying the trench. The cell... | 02/28/2006 |
| 7002850 | System and method for over erase reduction of nitride read only memory A nitride read only memory (NROM) erase system is disclosed. The NROM erase system comprises at least one memory sector, N sense amplifiers, and N buffers. The memory sector is segmented into N erase retry units according to the number of the sense amplifiers. One b... | 02/21/2006 |
| 7002210 | Semiconductor device including a high-breakdown voltage MOS transistor On a semiconductor substrate, a well is formed. In the well, one MOS transistor including a gate electrode, a source region, a source field limiting layer and a source/drain region, and another MOS transistor including a gate electrode, a drain electrode, a drain fi... | 02/21/2006 |
| 7001808 | Semiconductor integrated circuit device having a dummy conductive film and method of manufacturing the same Defects in element forming regions on which memory cells of a non-volatile memory are formed are to be diminished to reduce leakage current. End portions of element forming regions with non-volatile memory cells formed thereon are extended a length D by utilizing th... | 02/21/2006 |
| 7001809 | Method to increase coupling ratio of source to floating gate in split-gate flash A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with... | 02/21/2006 |
| 6998677 | Semiconductor component and method of manufacture A semiconductor component having a memory cell coupled to a trench line and a method for manufacturing the semiconductor component. Trenches having sidewalls are formed in a semiconductor substrate and a trench line is formed in each trench. A polysilicon insert is ... | 02/14/2006 |
| 6996009 | NOR flash memory cell with high storage density Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second... | 02/07/2006 |
| 6996007 | Apparatus and method of driving non-volatile DRAM A unit cell included in a non-volatile dynamic random access memory (NVDRAM) includes a control gate layer coupled to a word line; a capacitor for storing data; a floating transistor for transmitting stored data in the capacitor to a bit line, gate of the floating t... | 02/07/2006 |
| 6991988 | Static pass transistor logic with transistors with multiple vertical gates Static pass transistor logic having transistors with multiple vertical gates are described. Multiple vertical gates are edge defined with only a single transistor being required for multiple logic inputs. Thus a minimal surface area is required for each logic input.... | 01/31/2006 |
| 6989564 | Nonvolatile semiconductor storage apparatus and method of manufacturing the same A NOR type semiconductor storage comprising memory cells, word lines, local and main source lines of metal and bit lines is disclosed. Two adjacent cells on a column form one set and share the drain region. Two adjacent cell sets on a column share the source region.... | 01/24/2006 |
| 6985992 | Wear-leveling in non-volatile storage systems Methods and apparatus for performing wear leveling in a non-volatile memory system are disclosed. According to one aspect of the present invention, a method for allocating non-volatile memory that is divided into elements includes grouping the elements into a first ... | 01/10/2006 |
| 6979856 | Semiconductor memory device and control method and manufacturing method thereof A semiconductor memory device includes a first insulating film provided on a semiconductor substrate between first and second diffusion regions, a first gate electrode provided on the first insulating film, a second insulating film provided on the semiconductor subs... | 12/27/2005 |
| 6979857 | Apparatus and method for split gate NROM memory A split gate, vertical NROM memory cell is comprised of a plurality of oxide pillars that each has a source/drain region formed in the top of the pillar. A trench is formed between each pair of oxide pillars. A polysilicon control gate is formed in the trench betwee... | 12/27/2005 |
| 6979618 | Method of manufacturing NAND flash device A method of manufacturing a NAND flash device which can improve uniformity of disturb fail characteristics by performing an annealing process after an ion implantation process for forming a P well, reduce a fail bit count by performing an annealing process after an ... | 12/27/2005 |
| 6979859 | Flash memory cell and fabrication method Memory cells, formed as trench transistors, having a respective floating gate electrode and a control gate electrode at a trench wall above a channel region between doped regions for source and drain are provided with a gate electrode arranged in a further trench, v... | 12/27/2005 |
| 6977201 | Method for fabricating flash memory device A method for fabricating a flash memory includes forming a tunnel oxide layer by depositing a material with a conduction band energy level lower than that of SiO2 on a semiconductor substrate; forming a floating gate by depositing polysilicon on the tunne... | 12/20/2005 |
| 6977869 | Non-volatile memory and method of operation A method of programming and erasing an electrically erasable programmable read-only memory (EEPROM)device includes performing a band-to-band tunneling induced hot-electrons program and performing a Fowler-Nordheim tunneling erase. The EEPEOM device includes a P-type... | 12/20/2005 |
| 6975531 | 6F2 3-transistor DRAM gain cell A high density vertical three transistor memory cell is provided. The high density vertical three transistor memory cell is formed in a vertical pillar. The vertical pillar includes a first vertical transfer device having a source region, a drain region, and a body ... | 12/13/2005 |
| 6972620 | Post amplifier array integrated circuit An optical communication system that includes a multi-channel post amplifier assembly with flexible output configurations for amplifying optical-to-electrical converted signals on selectable groups of amplifier channels is provided. The post amplifier assembly, when... | 12/06/2005 |
| 6972995 | Imaging cell with a non-volatile memory that provides a long integration period and method of operating the imaging cell The image capture period of an imaging cell, or the total time that an imaging cell is exposed to light energy, is substantially increased by utilizing a non-volatile memory (NVM), such as an electrically-erasable, programmable, read-only-memory (EEPROM) structure. ... | 12/06/2005 |
