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Combination Beverage Container and Spittoon
A combination beverage container and spittoon includes a bottom portion including outer wall and a first inner wall defining a spittoon space.
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| Number | Title | Issue Date |
| 4734887 | Erasable programmable read only memory (EPROM) device and a process to fabricate thereof A structure of high packing density EPROM having floating gate type FET memory cells and a fabrication process thereof are disclosed. Marginal spaces for mask alignment and bird's beak in prior art EPROM device have been cut down by applying a self alignm... | 03/29/1988 |
| 4717943 | Charge storage structure for nonvolatile memories A four layer charge storage structure comprising alternate layers of silicon-rich silicon dioxide and silicon dioxide with electrode layers on top and bottom. The upper and middle silicon-rich layers act as enhanced Fowler-Nordheim injectors and the middl... | 01/05/1988 |
| 4694429 | Semiconductor memory device There is disclosed a semiconductor memory device comprising a memory cell connected to a bit line, and a clamp circuit comprising a load MOS transistor connected between a power source voltage and the bit line, for clamping the power source voltage and ap... | 09/15/1987 |
| 4688078 | Partially relaxable composite dielectric structure Unique EPROM and EEPROM devices are provided with a composite dielectric layer between the control gate and the floating gate which is sufficiently thick to provide electrical and physical integrity but also has a high equivalent dielectric constant. The ... | 08/18/1987 |
| 4613956 | Floating gate memory with improved dielectric The dielectric between the floating gate and the control gate, in an EEPROM or other floating gate memory is made by forming an oxide/nitride stack over the (first polysilicon) control gate. This dielectric not only provides a very high specific capacitan... | 09/23/1986 |
| 4545034 | Contactless tite RAM A transversly injected quasi-floating gate memory cell. A memory transistor in bulk silicon has a channel region in bulk silicon which is capacitatively coupled both to a thin polysilicon quasi-floating gate and to an overlying word line. The thin polysil... | 10/01/1985 |
| 4507758 | Semiconductor memory element with two field effect transistors This invention relates to a semiconductor memory element with two field effect transistors and an arrangement in which these elements are utilized. In accordance with the invention, a field effect transistor, transfer transistor Tt is provided ... | 03/26/1985 |
| 4500899 | Semiconductor memory device and process for producing the same The present invention is an improvement of a semiconductor memory device, preferably a PROM or a mask ROM, wherein: MOS transistors are formed in a semiconductor substrate, are arranged in rows, and are isolated from each other by a plurality of field ins... | 02/19/1985 |
| 4453174 | Semiconductor integrated circuit device with non-volatile semiconductor memory cells and means for relieving stress therein Disclosed is a metal oxide semiconductor integrated circuit device having an array of electrically rewritable, insulated gate type non-volatile semiconductor memory cells formed on a semiconductor substrate, read/write mode setting circuit and address des... | 06/05/1984 |
| 4434433 | Enhancement mode JFET dynamic memory A multiplicity of field effect type semiconductor memory elements are formed perpendicular to a surface of a semiconductor wafer. Charge carriers are transported in the semiconductor bulk perpendicular to the surface and a potential barrier is formed in t... | 02/28/1984 |
| 4412311 | Storage cell for nonvolatile electrically alterable memory A storage cell of a nonvolatile electrically alterable MOS memory (EAROM) comprises a p-type silicon substrate with n-doped drain and source areas interlinked by an n-channel which is partly overlain by a floating gate extending over part of the drain are... | 10/25/1983 |
| 4375087 | Electrically erasable programmable read only memory A floating gate tunneling metal oxide semiconductor (FATMOS) transistor is formed in a well region on a semiconductive substrate of a conductivity type opposite to that of the well region, so that charging and discharging of the FATMOS floating gate is ac... | 02/22/1983 |
| 4355455 | Method of manufacture for self-aligned floating gate memory cell A floating gate memory cell has its control gate self-aligned to the floating gate in the source to drain direction and its floating gate self-aligned to the channel region in that direction and the direction transverse thereto without overlaying the fiel... | 10/26/1982 |
| 4355375 | Semiconductor memory device A semiconductor memory device includes a plurality of floating gate transistors each of which comprises a semiconductor substrate, a first and second impurity doped region, channel region formed between the first and second impurity doped regions, a float... | 10/19/1982 |
| 4222063 | VMOS Floating gate memory with breakdown voltage lowering region A semiconductor electrically programmable read only memory device (EPROM) utilizes an array of memory cells each in the form of a single V-type MOSFET which achieves the normal AND function (Data-Word Address) using a capacitance coupled version of thresh... | 09/09/1980 |
| 4185319 | Non-volatile memory device A field-effect device with closed floating gate geometry suitable for use as a storage element in a non-volatile memory array.... | 01/22/1980 |
| 4173791 | Insulated gate field-effect transistor read-only memory array An array of read-only memory cells is formed from a plurality of insulated gate field-effect transistors. Information may be programmed into individual transistors within the array by application of selected potentials to the connecting lines of the array... | 11/06/1979 |
| 4173766 | Insulated gate field-effect transistor read-only memory cell A read-only memory cell formed from a single insulated gate field-effect transistor may be selectively programmed by being operated under suitable biasing conditions to cause some of the electrons flowing between the source and drain to acquire sufficient... | 11/06/1979 |
| 4126900 | Random access junction field-effect floating gate transistor memory JFET memory structures, in particular for RAM's with non-destructive reading-out of the charge state of a floating gate electrode in which the primary selection is realized by means of capacitive coupling with the floating gate electrode. The secondary se... | 11/21/1978 |
