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| Number | Title | Issue Date |
| 7428175 | Memory with a memory cell comprising a MOS transistor with an isolated body and method of accessing A dynamic random access memory (DRAM) including memory cells distributed in rows and in columns, each memory cell comprising a MOS transistor with a floating body, the memory comprising circuitry for writing a datum into a determined (i.e. selected) memory cell belo... | 09/23/2008 |
| 7423904 | Non-volatile semiconductor memory device and operating method thereof A non-volatile semiconductor memory device includes a memory cell array having a plurality of electrically-programmable non-volatile memory cells; a byte scan section detecting errors of said non-volatile memory cells per byte and outputting a status of pseudo-pass ... | 09/09/2008 |
| 7415646 | PageEXE erase algorithm for flash memory Methods of performing a sector erase of flash memory devices incorporating built-in self test circuitry are provided. The present invention employs an interactive verification and sector erase algorithm to verify and repeatedly erase the sector until a portion of th... | 08/19/2008 |
| 7411836 | Method of operating non-volatile memory A method of operating a non-volatile memory comprising a substrate, a gate, a charge-trapping layer, a source region and a drain region is provided. The charge-trapping layer close to the source region is an auxiliary charge region and the charge-trapping layer clos... | 08/12/2008 |
| 7411242 | Miniaturized virtual grounding nonvolatile semiconductor memory device and manufacturing method thereof The object of the present invention is to provide a new nonvolatile semiconductor memory device and its manufacturing method for the purpose of miniaturizing a virtual grounding type memory cell based on a three-layer polysilicon gate, enhancing the performance, and... | 08/12/2008 |
| 7411823 | In-service reconfigurable DRAM and flash memory device A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory cell is comprised of a vertical floating body transistor with dual gates, one on either side of a vertical p... | 08/12/2008 |
| 7405968 | Non-volatile memory cell using high-K material and inter-gate programming A non-volatile memory device has a channel region between source/drain regions, a floating gate, a control gate, a first dielectric region between the channel region and the floating gate, and a second dielectric region between the floating gate and the control gate... | 07/29/2008 |
| 7402850 | Back-side trapped non-volatile memory device Non-volatile memory devices and arrays are described that utilize back-side trapped floating node memory cells with band-gap engineered gate stacks with asymmetric tunnel barriers. Embodiments of the present invention allow for direct tunneling programming and effic... | 07/22/2008 |
| 7388777 | Semiconductor device A plurality of nonvolatile memory cells that constitute a nonvolatile memory are disposed in array form. Selection MIS•FETs for memory cell selection are electrically connected every bits. Each of the nonvolatile memory cells has a MIS•FET for writing data, a MI... | 06/17/2008 |
| 7388784 | Nonvolatile semiconductor memory device including memory cell units each having a given number of memory cell transistors A nonvolatile semiconductor memory device includes a plurality of memory cell units and a memory cell array in which the memory cell units are arranged in matrix. Each of the memory cell units has a given number of electrically writable and erasable memory cell tran... | 06/17/2008 |
| 7372098 | Low power flash memory devices A buried bipolar junction is provided in a floating gate transistor flash memory device. During a write operation electrons are injected into a surface depletion region of the memory cell transistors. These electrons are accelerated in a vertical electric field and ... | 05/13/2008 |
| 7372729 | High speed low voltage driver A high speed high and low voltage driver provides an output voltage without taxing a pumped voltage. The pumped voltage is used only when the output node has risen substantially to a supply voltage without draining the pumped voltage. ... | 05/13/2008 |
| 7369438 | Combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications A combination volatile and nonvolatile memory integrated circuit has at least one volatile memory array placed on the substrate and multiple nonvolatile memory arrays. The volatile and nonvolatile memory arrays have address space associated with each other such that... | 05/06/2008 |
| 7368781 | Contactless flash memory array A method for forming a contactless flash memory cell array is disclosed. According to an embodiment of the invention, a plurality of active regions is formed on a substrate. An insulating layer is then deposited over the active regions, and a portion of the insulati... | 05/06/2008 |
| 7368789 | Non-volatile programmable memory cell and array for programmable logic array A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be ... | 05/06/2008 |
| 7369435 | Write once read only memory employing floating gates Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate tra... | 05/06/2008 |
| 7369432 | Method for implementing a counter in a memory with increased memory efficiency A method for implementing a counter in memory, e.g., non-volatile memory such as flash memory. A first number of first binary values indicating a first portion of a current number of the counter in a binary field may be stored in a portion of memory. Storing the fir... | 05/06/2008 |
| 7366015 | Semiconductor integrated circuit device, production and operation method thereof A semiconductor integrated device having a plurality of memory cells, each including a floating gate, a control gate and an auxiliary gate formed over a side surface of the floating gate through an insulator film. Auxiliary gates coupled to selected memory cells fun... | 04/29/2008 |
| 7366012 | Synchronous memory device with reduced power consumption A synchronous non-volatile memory device that includes a circuit for performing operations on the memory device, a circuit for receiving a request of operation and operative information required for performing the operation in temporal succession, an activation circ... | 04/29/2008 |
| 7366025 | Reduced power programming of non-volatile cells Methods for minimizing current consumption in a memory array during programming of non-volatile memory cells, such as NROM cells, in the array include: programming a cell without having a direct current flowing from a positive supply to ground through the array, pro... | 04/29/2008 |
| 7363556 | Testing apparatus and testing method A testing apparatus for testing a memory-under-test includes a writing section for writing preset test data into each page of said memory-under-test to test said memory-under-test and a fail memory unit for storing the test result of said memory-under-test. The fail... | 04/22/2008 |
| 7362617 | Nonvolatile semiconductor memory device and method of rewriting data thereof The nonvolatile semiconductor memory device of the present invention includes a memory cell array wherein data is stored in a nonvolatile state based on a difference in memory information between two memory cells comprising a memory cell pair, and a writing controll... | 04/22/2008 |
| 7362615 | Methods for active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in t... | 04/22/2008 |
| 7362610 | Programming method for non-volatile memory and non-volatile memory-based programmable logic device A method for programming a flash memory cell comprises providing input data to the flash cell and providing a segmented programming pulse to the flash memory cell. The segmented programming pulse includes programming segments, each successive programming segment inc... | 04/22/2008 |
| 7359245 | Flash memory device having multi-level cell and reading and programming method thereof There is provided a flash memory device with multi-level cell and a reading and programming method thereof. The flash memory device with multi-level cell includes a memory cell array, a unit for precharging bit line, a bit line voltage supply circuit for supplying a... | 04/15/2008 |
| 7360137 | Flash programmer for programming NAND flash and NOR/NAND combined flash A method and system for implementing NAND programming of flash devices during in-circuit testing is described. A flash programmer may receive a program file from an in-circuit tester and device information from a NAND flash device, including information regarding ba... | 04/15/2008 |
| 7359250 | Twin insulator charge storage device operation and its fabrication method The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the pro... | 04/15/2008 |
| 7359241 | In-service reconfigurable DRAM and flash memory device A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory cell is comprised of a vertical floating body transistor with dual gates, one on either side of a vertical p... | 04/15/2008 |
| 7354825 | Methods and apparatus to form gates in semiconductor devices A method of formation a gate in a semiconductor device includes forming a gate oxide layer and a sacrificial layer on a semiconductor substrate. The sacrificial layer is then selectively etched to form a sidewall opening. Next, a polycrystalline silicon layer is for... | 04/08/2008 |
| 7355237 | Shield plate for limiting cross coupling between floating gates A memory system is disclosed that includes a set of non-volatile storage elements. Each of said non-volatile storage elements includes source/drain regions at opposite sides of a channel in a substrate and a floating gate stack above the channel. The memory system a... | 04/08/2008 |
| 7355238 | Nonvolatile semiconductor memory device having nanoparticles for charge retention A nonvolatile semiconductor memory device including a source region and a drain region formed on a surface of a semiconductor substrate, a channel-forming region formed so as to connect the source region and the drain region or so as to be sandwiched between the sou... | 04/08/2008 |
| 7352035 | Flash memory devices and methods for fabricating flash memory devices A flash memory device includes a cell string having a plurality of cell transistors connected in series, and a string selection transistor and a ground selection transistor connected to both ends of the cell string, respectively, wherein the cell transistor has a ch... | 04/01/2008 |
| 7351630 | Method of manufacturing flash memory device A method of manufacturing a flash memory device, including the steps of forming a gate on a semiconductor substrate in which a cell region, a source selection line region, and a drain selection line region are defined and then forming spacers on sidewalls of the gat... | 04/01/2008 |
| 7349260 | Alternate row-based reading and writing for non-volatile memory A set of storage elements is programmed beginning with a word line WLn adjacent a select gate line for the set. After programming the first word line, the next word line WLn+1 adjacent to the first word line is skipped and the next word line WLn+2 adjacent to WLn+1 ... | 03/25/2008 |
| 7345928 | Data recovery methods in multi-state memory after program fail A non-volatile memory device includes the ability to recover data in event of a program failure without having to maintain a copy of the data until the write is completed. As the integrity of the data can thus be maintained with having to save a copy, buffers can be... | 03/18/2008 |
| 7342272 | Flash memory with recessed floating gate A flash memory device where the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substr... | 03/11/2008 |
| 7342827 | Charge trap-type 3-level non-volatile semiconductor memory device and method of driving the same Disclosed herein is a charge trap-type 3-level non-volatile semiconductor memory device and method of driving the same. The charge trap-type 3-level non-volatile semiconductor memory device includes a memory array including a plurality of memory elements, each capab... | 03/11/2008 |
| 7341911 | Method of making EEPROM transistor pairs for block alterable memory A block alterable memory cell has a select control gate extending from a floating gate region to a drain region. The block alterable memory cell comprises a substrate layer that further includes a source implant region, a floating gate transistor region, and a drain... | 03/11/2008 |
| 7339231 | Semiconductor device and an integrated circuit card There is provided a technology capable of enhancing reliability in rewrite of storage information in a nonvolatile memory while checking an increase in area of a memory array thereof. With a memory array configuration, individual bit lines are connected to two memor... | 03/04/2008 |
| 7339820 | Nonvolatile memory and semiconductor device A nonvolatile memory capable of acting at each 1 bit and having a high integration density. A small-sized semiconductor device of multiple high functions having such nonvolatile memory. The nonvolatile memory is constructed to have a memory cell composed of t... | 03/04/2008 |
