Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 6917078 | One transistor SOI non-volatile random access memory cell One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various embodiments, the memory cell includes a substrate, a buried insulator layer formed on the substrate, and a transisto... | 07/12/2005 |
| 6917544 | Multiple use memory chip A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array. Each array may store Flash, EEPROM or both types of bits. ... | 07/12/2005 |
| 6917069 | Semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, and an array formed thereby, whereby each memory cell includes a trench formed into a surface of a semiconductor substrate, spaced apart source ... | 07/12/2005 |
| 6915175 | Method and device for programming nonvolatile semiconductor memory A control system includes a nonvolatile memory chip and a controller. The controller transfers a group of data from exterior to the nonvolatile memory chip based on the capacity of the nonvolatile memory, and enables the programming of the transferred data in the no... | 07/05/2005 |
| 6914813 | Segmented non-volatile memory array with multiple sources having improved source line decode circuitry A flash memory array arrangement having a plurality of erase blocks which can be separately erased. The erase blocks have separate source lines, the state of which is controlled by a source line decoder. In array read, program and erase operations, the source lines ... | 07/05/2005 |
| 6914811 | Method of driving one-time operable isolation elements and circuit for driving the isolation elements A method and a configuration for driving one-time operable isolation elements on a semiconductor chip store an item of isolation information for each isolation element to be operated on the chip. In which case, as soon as the isolation information item is present fo... | 07/05/2005 |
| 6914812 | Tunnel device level shift circuit A floating gate circuit has a level shift circuit. The floating gate circuit includes: a floating gate; a first and second tunnel device formed respectively between a first and second tunnel electrode; a first circuit coupled to the floating gate for generating an o... | 07/05/2005 |
| 6912161 | Nonvolatile semiconductor memory device In the nonvolatile semiconductor memory device of this invention, a program control circuit 1 sets the threshold value of a first reference cell RFC0 by means of a write circuit WC on the basis of a result of comparing the threshold value of the first ... | 06/28/2005 |
| 6909635 | Programmable memory cell using charge trapping in a gate oxide An illustrative embodiment of the present invention includes a non-volatile, reprogrammable circuit switch. The circuit switch includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a source region, a drain region, a cha... | 06/21/2005 |
| 6906952 | Nonvolatile semiconductor memory device and data writing method therefor In a nonvolatile semiconductor memory device wherein a plurality of threshold voltages are set so as to store multivalued information in one memory cell, data is first written into the memory cell whose threshold voltage is the lowest as a written state from the era... | 06/14/2005 |
| 6903367 | Programmable memory address and decode circuits with vertical body transistors Various embodiments provide a decoder for a memory array, comprising an array of address and output lines, vertical pillars, vertical floating gate transistors, and buried source lines. Each pillar includes single crystalline first and second contact layers separate... | 06/07/2005 |
| 6903974 | Flash memory device with a variable erase pulse A method of operating a flash memory device according to an embodiment of the present invention includes selecting a flash cell in a flash memory device to undergo an erase, applying a long erase pulse to the flash cell, and reading the flash cell. For each time the... | 06/07/2005 |
| 6903960 | Junction-isolated depletion mode ferroelectric memory devices Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various add... | 06/07/2005 |
| 6901006 | Semiconductor integrated circuit device including first, second and third gates In a semiconductor integrated circuit device including a third gate, the present invention improves miniaturization and operation speed and reduces a defect density of an insulator film. In a semiconductor integrated circuit device including a well of a first conduc... | 05/31/2005 |
| 6898126 | Method of programming a flash memory through boosting a voltage level of a source line A method of programming a flash memory through boosting a voltage level of a source line. The flash memory has n memory cell transistors cascaded in series, a local bit line positioned above the n memory cell transistors, a buried bit line positioned under the n mem... | 05/24/2005 |
| 6894925 | Flash memory cell programming method and system A flash memory cell programming system and method that facilitate efficient and quick operation of a flash memory cell by providing a biasable well (e.g., substrate) is presented. The biasable well flash memory cell enables increases in electrical field strengths in... | 05/17/2005 |
| 6894924 | Operating a non-volatile memory device An operation method of programming, erasing, and reading a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory device having a tunnel oxide layer thicker than 20 Å is provided. A program operation of the method is accomplished by applying a program vol... | 05/17/2005 |
| 6891751 | Charge trapping memory cell, method for fabricating it, and semiconductor memory device For particularly flexible and space-saving information storage, a charge trapping memory cell and a corresponding semiconductor memory device include a charge trapping gate configuration provided with a plurality of charge trapping gates each configured for substant... | 05/10/2005 |
| 6891220 | Method of programming electrons onto a floating gate of a non-volatile memory cell A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion ext... | 05/10/2005 |
| 6888749 | P-channel dynamic flash memory cells with ultrathin tunnel oxides Structures and methods involve dynamic enhancement mode p-channel flash memories with ultrathin tunnel oxide thicknesses. Both write and erase operations are performed by tunneling. The p-channel flash memory cell with thin tunnel oxides will operate on a dynamic ba... | 05/03/2005 |
| 6882582 | EEPROM circuit voltage reference circuit and method for providing a low temperature-coefficient voltage reference A voltage reference circuit (40) is provided for producing a low temperature-coefficient analogue trim value. A pair of EEPROMs (50 and 60) are arranged such that the trim value is the difference between two EEPROM transistor threshold voltages.... | 04/19/2005 |
| 6882577 | On-system programmable and off-system programmable chip An on-system programmable and off-system programmable chip comprises a control circuit connected to an on-system programmable nonvolatile memory and an off-system programmable nonvolatile memory, and a pumping circuit connected to the on-system programmable nonvolat... | 04/19/2005 |
| 6882573 | DMOS device with a programmable threshold voltage A DMOS device is provided which is equipped with a floating gate having a first and second electrode in close proximity thereto. The floating gate is separated from one of the first and second electrodes by a thin layer of dielectric material whose dimensions and co... | 04/19/2005 |
| 6879517 | Battery circuit with three-terminal memory device This invention includes a memory device having exactly three external terminals: a power external terminal; a ground or return external terminal; and a one-wire data communication external terminal. The memory is preferably employed in a rechargeable battery pack ha... | 04/12/2005 |
| 6870764 | Floating gate analog voltage feedback circuit A floating gate circuit in a read mode that includes at least one floating gate and an analog feedback circuit is disclosed. The feedback circuit causes the floating gate circuit to reach a steady state condition in the read mode such that a reference voltage is gen... | 03/22/2005 |
| 6870763 | Electrically alterable non-volatile memory with n-bits per cell An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell can be performed without actually reading the memory state of the cell during the programming operation. A plurality of th... | 03/22/2005 |
| 6868473 | Non-volatile memory access control A system is described for controlling access to non-volatile memory. The system can include logic configured to determine whether to delay access to the non-volatile memory. ... | 03/15/2005 |
| 6853572 | Methods and apparatuses for a ROM memory array having twisted source or bit lines Various methods, apparatuses, and systems in which a read only memory is arrayed in a multiple rows and columns. A first column of memory cells is organized into groups of memory cells including a first group of memory cells and a second group of memory cells. A fir... | 02/08/2005 |
| 6850440 | Method for improved programming efficiency in flash memory cells A method of operating a non-volatile memory device includes providing the non-volatile memory device with a body of first conductivity, a source region of second conductivity, a drain region of second conductivity on the body, and a control gate over the body adjace... | 02/01/2005 |
| 6847557 | Method of erasing non-volatile memory data A method of erasing non-volatile memory data. The erasing method includes applying a first voltage to a substrate, applying a second voltage to a control gate and setting both source terminal and drain terminal to a floating state during a first time interval so tha... | 01/25/2005 |
| 6845044 | Method of preventing high Icc at start-up in zero-power EEPROM cells for PLD applications A CMOS memory cell (FIG. 1) is provided which includes a PMOS transistor (102) and an NMOS transistor (104) with a common floating gate and common drains configured to prevent a large drain of Icc current from a power supply during power-up. To ... | 01/18/2005 |
| 6844584 | Memory cell, memory cell configuration and fabrication method Each memory cell is a memory transistor which is provided on a top side of a semiconductor body and has a gate electrode which is arranged in a trench located between a source region and a drain region that are formed in the semiconductor material. The gate electrod... | 01/18/2005 |
| 6845039 | Programming methods for multi-level flash EEPROMS A method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a thres... | 01/18/2005 |
| 6842380 | Method and apparatus for erasing memory The present invention provides a method and apparatus for erasing memory blocks. The apparatus includes a first plurality of memory cells formed in a substrate and a second plurality of memory cells formed in the substrate. The apparatus further includes a bias circ... | 01/11/2005 |
| 6836430 | Extraction of a binary code based on physical parameters of an integrated circuit An extraction method and an integrated cell for extracting a binary value based on a propagation of an edge of a triggering signal in two electric paths, including across two voltage supply terminals: two parallel branches each including, in series, a resistor for d... | 12/28/2004 |
| 6829166 | Method for controlling a non-volatile dynamic random access memory A method for controlling a non-volatile dynamic random access memory provides a non-volatile dynamic random access memory having a storage unit and a control unit. The storage unit has a floating gate for storing charges and a control gate for receiving an operating... | 12/07/2004 |
| 6822888 | Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric A semiconductor memory cell having a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level ... | 11/23/2004 |
| 6819594 | Electrically erasable programmable logic device An electrically erasable programmable logic device includes a P-type substrate, a first N-type doped region located inside the P-type substrate, and a first gate located on the P-type substrate. The first gate is adjacent to the first N-type doped region, is in a fl... | 11/16/2004 |
| 6815322 | Fabrication method of semiconductor device The present invention provides a technology capable of shortening a TAT of a microcomputer with a nonvolatile memory built therein and achieving a reduction in cost. Flash ROMs comprising memory cells each substantially identical in structure to each of memory cells... | 11/09/2004 |
| 6808169 | Non-volatile memory with crown electrode to increase capacitance between control gate and floating gate A non-volatile memory (NVM) system includes a NVM cell having: a semiconductor region having a first conductivity type; a gate dielectric layer located over the semiconductor region; a gate electrode located over the gate dielectric layer; a source region and a drai... | 10/26/2004 |
