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| Number | Title | Issue Date |
| 8159873 | Semiconductor integrated circuit There is provided a semiconductor integrated circuit including a state detection enhancement circuit which includes an input terminal and an output terminal and has a function of generating an electric potential of a magnitude capable of performing nonvolatile memor... | 04/17/2012 |
| 8125824 | Nanotube random access memory (NRAM) and transistor integration A nanotube random access memory (NRAM) structure is provided. The structure includes a substrate, a gate electrode disposed in the substrate, and a first nanotube fabric disposed on the substrate. The first nanotube fabric has a channel region spaced apart from the ... | 02/28/2012 |
| 7826261 | Semiconductor memory device, method of writing data therein, and method of reading data therefrom A semiconductor memory device (1) has a FET (10) (first field-effect transistor), a FET (20) (second field-effect transistor), a contact plug (32) (first conductive plug), contact plugs (34) (second conductive plugs), and a detecti... | 11/02/2010 |
| 7675771 | Capacitor-less DRAM circuit and method of operating the same One embodiment includes a plurality of word lines, a plurality of source lines, a plurality of bit lines intersecting with the plurality of word lines, and a plurality of memory cells formed at intersections of the plurality of word lines and the plurality of bit li... | 03/09/2010 |
| 7548456 | Combo memory cell A combo memory cell having a SRAM cell and a mask-ROM code programmer. The SRAM cell comprises first and second inverters. The first inverter comprises a first PMOS transistor and a first NMOS transistor. Gates of the first PMOS and NMOS transistors are commonly con... | 06/16/2009 |
| 7417288 | Substrate solution for back gate controlled SRAM with coexisting logic devices A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devic... | 08/26/2008 |
| 7414896 | Technique to suppress bitline leakage current Methods and apparatus that may help reduce standby current in memory devices are provided. By separating equalizing and precharging functions into separate circuit structures, current paths between a source of precharge voltage and a defective wordline (e.g., having... | 08/19/2008 |
| 7405967 | Microelectronic programmable device and methods of forming and programming the same A microelectronic programmable structure and methods of forming and programming the structure are disclosed. The programmable structure generally include an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applyin... | 07/29/2008 |
| 7391640 | 2-transistor floating-body dram A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during tim... | 06/24/2008 |
| 7382650 | Method and apparatus for sector erase operation in a flash memory array A memory device is provided which includes a substrate, a common P-well isolated from the substrate, a plurality of sectors, and a common sector selection transistor configured to select one of the sectors for erasure. Each of the sectors share the same common secto... | 06/03/2008 |
| 7372065 | Programmable metallization cell structures including an oxide electrolyte, devices including the structure and method of forming same A microelectronic programmable structure suitable for storing information, a device including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrod... | 05/13/2008 |
| 7368789 | Non-volatile programmable memory cell and array for programmable logic array A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be ... | 05/06/2008 |
| 7358797 | Semiconductor device having secure operating characteristic under low power environment Provided is a semiconductor device that can secure a current consumption characteristic and an operating speed characteristic under a low power voltage environment. The semiconductor device is divided into a plurality of regions depending on the current consumption ... | 04/15/2008 |
| 7354821 | Methods of fabricating trench capacitors with insulating layer collars in undercut regions Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the firs... | 04/08/2008 |
| 7352642 | Semiconductor memory device A semiconductor memory device includes a memory cell including a floating body region and storing data on the basis of the amount of charges in the floating body region; word lines; a counter cell array including counter cells provided to correspond to the word line... | 04/01/2008 |
| 7348640 | Memory device A memory capable of reducing the memory cell size is provided. In this memory, a first gate electrode of a first selection transistor and a second gate electrode of a second selection transistor are provided integrally with a word line, and arranged to obliquely ext... | 03/25/2008 |
| 7342279 | Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than tw... | 03/11/2008 |
| 7339842 | Timing control for sense amplifiers in a memory circuit An integrated circuit 18 includes a memory 20 having timing circuitry formed of a global controller 26 and a self-timing path for triggering the sense amplifiers 28 to read bit lines 30 within the array of bit cells 24. The ... | 03/04/2008 |
| 7329583 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 02/12/2008 |
| 7321274 | RF switch A RF switch can be used in a wide frequency range and can be manufactured at a low cost. The RF switch changes a signal passing through a waveguide with a variable device that is switchable between the first state in which the variable device has a high resistance a... | 01/22/2008 |
| 7320131 | Methods and apparatus for selecting a server to process a request The invention is directed to techniques for selecting a resource from several resources to process a request from a client. A client sends the request to a data communications device (e.g., network device or switch), which measures usage information from usage meter... | 01/15/2008 |
| 7319614 | Non-volatile semiconductor memory device and data programming method In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispers... | 01/15/2008 |
| 7307877 | Natural analog or multilevel transistor DRAM-cell Circuits and methods to design and to fabricate said circuits to accomplish a two-level DRAM cell or a multilevel DRAM cell using a natural transistor have been achieved. The usage of a natural transistor, having a threshold voltage of close to zero, as a pass trans... | 12/11/2007 |
| 7301821 | Volatile data storage in a non-volatile memory cell array A method for storing data on nodes in memory cells of a non-volatile memory cell array including steps of setting non-volatile devices of the non-volatile memory cell array to a desired state, biasing pull-up devices and non-volatile devices in a first set of rows o... | 11/27/2007 |
| 7301197 | Non-volatile nanocrystal memory transistors using low voltage impact ionization A low voltage non-volatile charge storage transistor has a nanocrystal layer for permanently storing charge until erased. A subsurface charge injector generates secondary carriers by stimulating electron-hole current flowing toward the substrate, with some carriers ... | 11/27/2007 |
| 7294882 | Non-volatile memory with asymmetrical doping profile Stacked gate structures for a NAND string are created on a substrate. Source implantations are performed at a first implantation angle to areas between the stacked gate structures. Drain implantations are performed at a second implantation angle to areas between the... | 11/13/2007 |
| 7291881 | Bit line structure and method of fabrication The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which conta... | 11/06/2007 |
| 7285818 | Non-volatile two-transistor programmable logic cell and array layout A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transisto... | 10/23/2007 |
| 7286414 | Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals may be dependent upon the levels of programming reference signals used for controll... | 10/23/2007 |
| 7282770 | Semiconductor device and fabrication process thereof A semiconductor device includes a semiconductor substrate of a first conductivity type, a well of the first conductivity type formed in the semiconductor substrate, a transistor formed in the well, a diffusion region of a second conductivity type formed in the semic... | 10/16/2007 |
| 7279378 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/09/2007 |
| 7279368 | Method of manufacturing a vertical junction field effect transistor having an epitaxial gate A vertical junction field effect transistor includes a trench formed in an epitaxial layer. The trench surrounds a channel region of the epitaxial layer. The channel region may have a graded or uniform dopant concentration profile. An epitaxial gate structure is for... | 10/09/2007 |
| 7276431 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/02/2007 |
| 7271436 | Flash memory devices including a pass transistor Flash memory integrated circuit devices include an integrated circuit substrate. A cell array on the integrated circuit substrate includes a plurality of cell transistors. A bit line is coupled to ones of the plurality of cell transistors and a first pass transistor... | 09/18/2007 |
| 7269062 | Gated diode nonvolatile memory cell A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of... | 09/11/2007 |
| 7268042 | Nonvolatile semiconductor memory and making method thereof A nonvolatile semiconductor memory device of a split gate structure having a gate of low resistance suitable to the arrangement of a memory cell array is provided. When being formed of a side wall spacer, a memory gate is formed of polycrystal silicon and then repla... | 09/11/2007 |
| 7266020 | Method and apparatus for address and data line usage in a multiple context programmable logic device A method and apparatus to provide triple modular redundancy (TMR) in one mode of operation, while providing multiple context selection during a second mode of operation. Intelligent voting circuitry facilitates both modes of operation, while further enhancing the ro... | 09/04/2007 |
| 7262997 | Process for operating an electronic device including a memory array and conductive lines An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of di... | 08/28/2007 |
| 7259640 | Miniature RF and microwave components and methods for fabricating such components RF and microwave radiation directing or controlling components are provided that may be monolithic, that may be formed from a plurality of electrodeposition operations and/or from a plurality of deposited layers of material, that may include switches, inductors, ant... | 08/21/2007 |
| 7257022 | Nanocrystal write once read only memory for archival storage Structures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a first source/drain region, a se... | 08/14/2007 |
