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| Number | Title | Issue Date |
| 7656702 | Ultra low voltage, low leakage, high density, variation tolerant memory bit cells Methods and apparatus to provide ultra low voltage, low leakage, high density, and/or variation tolerant memory bit cells are described. In one embodiment, each of the cross-coupled invertors of a memory cell may include a plurality of p-channel transistors. Other e... | 02/02/2010 |
| 7382667 | Active termination circuit and method for controlling the impedance of external integrated circuit terminals An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of ... | 06/03/2008 |
| 7372748 | Voltage regulator in a non-volatile memory device System and method for controlling voltage in a non-volatile memory system is provided. The system includes a voltage regulator that monitors an output voltage (VDD) and a mirror voltage (Vmirror). When the voltage VDD is greater than the voltage Vmirror beyond a thr... | 05/13/2008 |
| 7359229 | Semiconductor memory device and method of operating same There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this ... | 04/15/2008 |
| 7310266 | Semiconductor device having memory cells implemented with bipolar-transistor-antifuses operating in a first and second mode A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing inform... | 12/18/2007 |
| 7304327 | Thyristor circuit and approach for temperature stability Switching operations, such as those used in memory devices, are enhanced using a semiconductor device having a thyristor adapted to switch between conducting and blocking states and operate at low power. According to an example embodiment of the present invention, t... | 12/04/2007 |
| 7272031 | Method and apparatus for reduced power cell The invention relates to reduced power cells. Some embodiments of the invention provide a memory circuit that has a storage cell. The storage cell contains several electronic components and an input. The electronic components receive a reduced voltage from the input... | 09/18/2007 |
| 7245521 | Semiconductor integrated circuit device The present invention provides a semiconductor integrated circuit device having an SRAM in which leak current is reduced. In an SRAM comprising a plurality of memory cells each constructed by a storage in which input and output terminals of two inverter circuits are... | 07/17/2007 |
| 7236001 | Redundancy circuits hardened against single event upsets A decision block is incorporated into a circuit design to provide hardening against single event upset and to store data. The decision block includes a storage element that stores data as long as inputs to the decision block remain constant. The decision block recei... | 06/26/2007 |
| 7236773 | Conference call method and apparatus therefor A conference call facility is described in which one (2a) of a group of communication devices (2a,2b,2c,2d) connected to a low power radio frequency network (9) is able to set up a call to ... | 06/26/2007 |
| 7227211 | Decoupling capacitors and semiconductor integrated circuit VSS 302 is provided to a gate portion 304 and VDD 301 is provided to a source portion 305 and a drain portion 306 of a MOS transistor which constitutes a decoupling capacitor, and a potential NWVDD 303 different from that pr... | 06/05/2007 |
| 7211867 | Thin film memory, array, and operation method and manufacture method therefor A memory cell which is formed on a fully depleted SOI or other semiconductor thin film and which operates at low voltage without needing a conventional large capacitor is provided as well as a memory cell array. The semiconductor thin film is sandwiched between firs... | 05/01/2007 |
| 7187601 | Active termination circuit and method for controlling the impedance of external integrated circuit terminals An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of ... | 03/06/2007 |
| 7187581 | Semiconductor memory device and method of operating same There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this ... | 03/06/2007 |
| 7173627 | Apparatus, method and system with a graphics-rendering engine having a graphics context manager A method, apparatus, and system to concurrently render independent images for display on one or more display devices. In an embodiment, a graphics-rendering engine concurrently renders independent images for display on multiple display devices. A graphics context ma... | 02/06/2007 |
| 7171599 | Field programmable device A field programmable device is disclosed, including a plurality of logic blocks; a plurality of connections connecting the logic blocks; configuration circuitry for outputting configuration data for programming the field programmable device, the configuration circui... | 01/30/2007 |
| 7161404 | Single event upset hardened latch A hardened latch capable of providing protection against single event upsets (SEUs) is disclosed. The hardened latch includes a first latch and a second latch that mirrors a subset of gates of the first latch. The second latch is inserted in the feedback path of the... | 01/09/2007 |
| 7145808 | Nonvolatile semiconductor memory apparatus and method of producing the same A nonvolatile semiconductor memory apparatus suitable to logic incorporation, by which a charge injection efficiency is high and hot electrons (HE) can be effectively injected at a low voltage is provided. A memory transistor (M) comprises first and second source/dr... | 12/05/2006 |
| 7106638 | Active termination circuit and method for controlling the impedance of external integrated circuit terminals An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of ... | 09/12/2006 |
| 7106619 | Graphics controller integrated circuit without memory interface A graphics controller system which has a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video sig... | 09/12/2006 |
| 7085153 | Semiconductor memory cell, array, architecture and device, and method of operating same There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of the inven... | 08/01/2006 |
| 7085156 | Semiconductor memory device and method of operating same There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this ... | 08/01/2006 |
| 7080234 | VLIW computer processing architecture having the problem counter stored in a register file register According to the invention, a processing core (12) comprising a processing pipeline (100) having N-number of processing paths (56), each of which process instructions (54) on M-bit data words. In addition, the processing core (12) ... | 07/18/2006 |
| 7075834 | Semiconductor integrated circuit device A semiconductor device includes signal lines over which signals are transferred, and a drive circuit driving the signal lines in operating modes. The operating modes include a dynamic operation mode in which the signal lines are precharged, and a static operation mo... | 07/11/2006 |
| 7027346 | Bit line control for low power in standby The present invention achieves technical advantages as embodiments of an SRAM cell (20, 30) having the bit line voltage (BLB/BLB) controlled during standby, such as allowing the bit line to float allowing the bit line voltage to be established by balance of l... | 04/11/2006 |
| 6998655 | Semiconductor device comprising memories on the inside and outside of bonding pad A semiconductor integrated circuit is capable of filling the need for more memory space through the effective use of an already-designed core block. A block (1) including a CPU, an array (4a) of a plurality of bonding pads, and RAMs (21 | 02/14/2006 |
| 6981231 | System and method to reduce leakage power in an electronic device A system and method to reduce leakage power consumption of electronic devices. In addition to assigning threshold voltages, sizes of the transistors within the device may be varied to provide a range of options to meet the timing requirements while minimizing the le... | 12/27/2005 |
| 6977410 | Test mode decoder in a flash memory Embodiments of the present invention include an interface circuit to put an integrated circuit into a test mode and a decoder to decode one or more commands provided to the integrated circuit. The decoder includes sub-circuits, and each sub-circuit has a number of t... | 12/20/2005 |
| 6944071 | Active termination circuit and method for controlling the impedance of external integrated circuit terminals An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of ... | 09/13/2005 |
| 6944042 | Multiple bit memory cells and methods for reading non-volatile data Memory cells are disclosed comprising volatile and non-volatile portions, where the non-volatile portions provide storage of multiple non-volatile data states or bits per memory cell. Methods are provided for reading non-volatile data states from a non-volatile port... | 09/13/2005 |
| 6937053 | Single event hardening of null convention logic circuits A system and method for hardening a Null Convention Logic (NCL) circuit against Single Event Upset (SEU) is presented. Placing a resistive element into a feedback loop of the NCL circuit may harden the NCL circuit. A bypass element may be placed in parallel with the... | 08/30/2005 |
| 6920077 | Graphics controller integrated circuit without memory interface A CMOS integrated circuit which has a graphics controller system that has a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video strea... | 07/19/2005 |
| 6903733 | Ultra-high bandwidth multi-port memory system for image scaling applications The image scaling memory system of the present invention eliminates the use of internal or external line memories by using an existing frame memory coupled with an input buffer and a plurality of output buffers for providing a vertical scalar with simultaneous paral... | 06/07/2005 |
| 6809957 | Memory cells enhanced for resistance to single event upset Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity mo... | 10/26/2004 |
| 6714436 | Write operation for capacitorless RAM A method for writing data to single-transistor capacitorless (1T/0C) RAM cell, wherein the cell structure is predicated on an SOI MOS transistor that has a floating body region (12). Data is written to the cell by the instigation of band-to-band tunneling (BT... | 03/30/2004 |
| 6657906 | Active termination circuit and method for controlling the impedance of external integrated circuit terminals An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The imp... | 12/02/2003 |
| 6643167 | Semiconductor memory A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists ... | 11/04/2003 |
| 6614078 | Highly latchup-immune CMOS I/O structures CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n... | 09/02/2003 |
| 6577522 | Semiconductor memory device including an SOI substrate A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region ... | 06/10/2003 |
| 6560142 | Capacitorless DRAM gain cell A nondestructive read, two-device gain cell for a DRAM memory, based on conventional complementary metal oxide technology is disclosed. The charge is stored on the gate of a first MOSFET, with a second MOSFET connected to the gate for controlling the char... | 05/06/2003 |
