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| Number | Title | Issue Date |
| 7335965 | Packaging of electronic chips with air-bridge structures A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A circuit assembly comprises an electronic chip and a conductive structur... | 02/26/2008 |
| 7002841 | MRAM and methods for manufacturing and driving the same An MRAM having improved integration density and ability to use a magnetic tunneling junction (MTJ) layer having a low MR ratio, and methods for manufacturing and driving the same, are disclosed. The MRAM includes a semiconductor substrate having a bipolar junction t... | 02/21/2006 |
| 6961262 | Memory cell isolation Device and method for memory cell isolation. The memory cell includes a resistive component, such as a magnetic random access memory (MRAM) cell, and an isolation component, such as a four-layer diode. The memory cell may be included in a memory array. The method in... | 11/01/2005 |
| 6801450 | Memory cell isolation Device and method for memory cell isolation. The memory cell includes a resistive component, such as a magnetic random access memory (MRAM) cell, and an isolation component, such as a four-layer diode. The memory cell may be included in a memory array. The method in... | 10/05/2004 |
| 6535435 | Reference voltage generator permitting stable operation A reference voltage generation circuit is provided which includes a p-channel type MOSFET used as an input transistor to allow a sufficient current to flow through a differential amplifier even if the threshold voltages of MOSFETs used in the differential... | 03/18/2003 |
| 6292390 | Semiconductor device A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition IBE | 09/18/2001 |
| 5966324 | Static semiconductor memory device driving bit line potential by bipolar transistor shared by adjacent memory cells Memory cells which are adjacent to each other along a column direction share a bipolar transistor driving the potential level of a corresponding bit line. Other memory cells which are adjacent to each other in the column direction share another bipolar tr... | 10/12/1999 |
| 5661681 | Semiconductor memory and method of writing, reading, and sustaining data thereof A semiconductor memory has bit lines, word lines, ground lines, and memory cells. The bit lines intersect the word and ground lines, to form intersections where the memory cells are arranged, respectively. Each of the memory cells consists of a double-emi... | 08/26/1997 |
| 5646897 | Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels A logic circuit is provided for a memory device which can be operated at a high speed with a lower voltage power source level than conventional devices. This logic circuit can be used in a multi-bit test circuit executing the wired-OR-logic operation of c... | 07/08/1997 |
| 5574683 | Memory device and a method for writing information in the memory device A memory device comprises a row address signal line Ax, a pair of column address signal lines Ay1, Ay2, a standby signal line Sb, a memory cell provided at an area where the row address signal line Ax intersects with the column address signal lines Ay1, A... | 11/12/1996 |
| 5491654 | Static random access memory device having thin film transistor loads In a static random access memory device where thin film transistors are used memory cell loads, first and second semiconductor layers having source regions, channel regions and drain regions of the thin film transistors partly oppose first and second cond... | 02/13/1996 |
| 5383153 | Semiconductor memory device with flash-clear function A semiconductor memory device equipped with a flash-clear function has a plurality of flip-flop type memory cells each of which is formed by a first multi-emitter transistor and a second multi-emitter transistor, a clear line and a switching circuit. Each... | 01/17/1995 |
| 5311465 | Semiconductor memory device that uses a negative differential resistance A semiconductor memory device comprises a memory cell transistor that includes two active parts each including therein an emitter and a base and showing a negative differential resistance. The collector layer is shared commonly by the two active parts and... | 05/10/1994 |
| 5287303 | SCR type memory apparatus An SCR type memory apparatus which is short in access time, easy in setting current values upon reading and writing and easy in constructing a peripheral circuit with less power supply voltage limitation is described. The semiconductor memory apparatus co... | 02/15/1994 |
| 5276638 | Bipolar memory cell with isolated PNP load A bipolar memory array and memory cell. The memory cell has a pair of cross coupled NPN storage transistors and a pair of PNP load transistors. The collector of each of the load transistors is connected to one of the storage transistors. A base, common to... | 01/04/1994 |
| 5255225 | Semiconductor integrated circuit device and memory consisting of semiconductor integrated circuit A semiconductor integrated circuit device including a level conversion circuit in which the simplifying of the circuit and the increasing of the speed of operation have been attained is provided. A pair of complementary output signals amplified to a required s... | 10/19/1993 |
| 5218567 | Match detection circuit for cache memory apparatus A cache memory apparatus made up of a memory cell array (300) and a match detection circuit is disclosed. The match detection circuit produces a detection signal related to whether a search data coincides with a data read out of the memory cell array (300... | 06/08/1993 |
| 5216630 | Static semiconductor memory device using bipolar transistor Disclosed is a bipolar SRAM including, in each memory cell, two NPN multiemitter transistors, with a base of one transistor being cross-connected to a collector of the other transistor. The respective collectors of these two multiemitter transistors in an... | 06/01/1993 |
| 5200924 | Bit line discharge and sense circuit A bit line discharge and sense circuit is provided for use with a static RAM that includes a row and column array of memory cells addressable via first and second bit lines and also a row select line. Each memory cell includes a transistor pair, wherein t... | 04/06/1993 |
| 5189640 | High speed, multi-port memory cell utilizable in a BICMOS memory array A multi-port memory cell utilizes a storage cell to define complementary data storage nodes. Each read port of the memory cell includes two FETs respectively coupled between one of a pair of complementary data-out lines and a read enable line to isolate t... | 02/23/1993 |
| 5179538 | Memory system including CMOS memory cells and bipolar sensing circuit A memory system (10) is disclosed including a memory array (14), decoder circuit (16), and sensing circuit (17). The memory array includes a plurality of two-port CMOS memory cells (42) arranged in columns and rows that are selectively addressed by the de... | 01/12/1993 |
| 5172340 | Double stage bipolar sense amplifier for BICMOS SRAMS with a common base amplifier in the final stage There is described a double stage sense amplifier (4) in bipolar technology achieving very high speed operation without saturation or connection problems. For each memory cell column of the computer member system (1), a first stage or column sense stage (... | 12/15/1992 |
| 5121357 | Static random access split-emitter memory cell selection arrangement using bit line precharge This invention relates generally to the static, random access, semiconductor memory arrays which incorporate split-emitter memory cells. The latter are accessed during a read cycle of a selected memory cell by precharging all the bit lines of unselected m... | 06/09/1992 |
| 5117391 | Bipolar memory cell array biasing technique with forward active PNP load cell A bipolar memory array arranged in a row and column matrix is responsive to a plurality of word line driver transistors for selecting one row of memory cells thereof. The current flowing through each memory cell is provided by a pair or lateral PNP transi... | 05/26/1992 |
| 5083292 | Bipolar random access memory A bipolar random access memory comprises a plurality of memory cells arranged in row and column formation, a plurality of word lines provided in correspondence to respective rows of the memory cells, a plurality of bit lines provided in correspondence to ... | 01/21/1992 |
| 5043939 | Soft error immune memory An alpha radiation immune integrated circuit memory cell has a pair of secondary transistors connected to cross-couple the primary transistors to form a flow, secondary storage node. The secondary transistors are biased to a standby current that, in combi... | 08/27/1991 |
| 5029127 | Bipolar SRAM having word lines as vertically stacked pairs of conductive lines parallelly formed with holding current lines There is implemented memory cells and corresponding signal lines associated therewith in bipolar type static random access memories employing wirings of multi-layer construction for transmitting a common signal therethrough such as with respect to the ind... | 07/02/1991 |
| 5029129 | High-speed bipolar memory system A switched load diode cell has been developed wherein first and second multi-emitter NPN transistors are provided having bases cross coupled to the other's collectors in typical latch fashion as shown in FIG. 5. A PN diode is provided having an anode coup... | 07/02/1991 |
| 4964081 | READ-WHILE-WRITE RAM CELL A READ-WHILE-WRITE current-mode logic RAM cell suitable for use in a RAM device having the ability to simultaneously write and read data. The RAM cell contains a bit-cell consisting of flip-flop configured transistors differentially connected to a constant cur... | 10/16/1990 |
| 4926378 | Bipolar static RAM having two wiring lines for each word line There is implemented memory cells and corresponding signal lines associated therewith in bipolar type static random access memories employing wirings of multi-layer construction for transmitting a common signal therethrough such as with respect to the ind... | 05/15/1990 |
| 4899311 | Clamping sense amplifier for bipolar ram A sense amplifier is provided for a bipolar random access memory that has memory cells arranged in a column and a pair of bit lines for said column of memory cells. A first bipolar transistor has its collector-emitter path coupled to one of the bit lines ... | 02/06/1990 |
| 4864539 | Radiation hardened bipolar static RAM cell This invention relates generally to Static Random Access Memory (SRAM) cells and more particularly, relates to a SRAM cell wherein soft-error due to -particle radiation is reduced by permitting the potential at the common-emitter node of the cross-... | 09/05/1989 |
| 4864540 | Bipolar ram having no write recovery time A bipolar random access memory having no write recovery time. During a data write operation, while the memory state of the memory cell is being shifted, a data bypass circuit sets a sense latch in the sense amplifier to store the new state to which the me... | 09/05/1989 |
| 4858183 | ECL high speed semiconductor memory and method of accessing stored information therein A hybrid ECL memory includes a hybrid memory array 36 which utilizes cross coupled CMOS latches (70). Each CMOS latch (70) is accessed by an ECL decoder (40) and an ECL Word Line driver (42) to read data therefrom. Data is accessed through a bipolar trans... | 08/15/1989 |
| 4823315 | Plural emitter memory with voltage clamping plural emitter transistor A transistor memory cell device comprising a pair of cross-coupled transistors constituting storage elements for storing binary information and having column drive emitter inputs to which a relatively high column drive current is applied for the selective... | 04/18/1989 |
| 4788662 | Semiconductor memory device using resonant-tunneling hot electron transistor A semiconductor memory device comprises an address line, a write line, a read line, and a memory cell connected to the address, write and read lines, where the memory cell comprises a power source, an RHET, a switching element and a data transfer element.... | 11/29/1988 |
| 4783765 | Bipolar memory cell with cross-connected transistors and an external capacitance An integrated bipolar memory cell with random access, includes an upper word line, a lower word line, two bit lines, two transistors each having two emitters, a base and a collector fed back crosswise to the base of the other transistor, two Schottky diod... | 11/08/1988 |
| 4769785 | Writing speed of SCR-based memory cells Load resistors are connected in series between the PNP portions of the SCRs and the upper word-line. The load presented to the NPN portions of the SCRs is thus a composite formed of a PNP transistor in series with a resistor. The resistor causes a downwar... | 09/06/1988 |
| 4747083 | Semiconductor memory with segmented word lines A semiconductor memory device including at least word lines and bit lines with memory cells located at each cross point therebetween. Each of the word lines is divided to form segmented word lines and each of the word line segments is driven by an individ... | 05/24/1988 |
| 4745580 | Variable clamped memory cell An improved memory cell circuit in which the collector of the "ON" transistor is clamped to a variable voltage level to prevent saturation. Saturation is prevented by providing a mechanism for limiting the voltage between a first node in the word line cir... | 05/17/1988 |
