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| Number | Title | Issue Date |
| 8184477 | Semiconductor switching device A switching device and methods of making and operating the same are provided. In one aspect, a method of operating a switching device is provided that includes providing a MOS transistor that has a gate, a source region, a drain region and a body region. A bipolar t... | 05/22/2012 |
| 8134867 | Memory array having a programmable word length, and method of operating same A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistor... | 03/13/2012 |
| 8125823 | Method and structure for ultra-high density, high data rate ferroelectric storage disk technology using stabilization by a surface conducting layer A method and structure for a ferroelectric storage medium, includes a metallic underlayer and a ferroelectric data layer over the metallic underlayer. A layer over the ferroelectric data layer has a charge migration rate faster than a charge migration rate of the fe... | 02/28/2012 |
| 8116130 | Integrated circuits with nonvolatile memory elements Nonvolatile memory element circuitry is provided that is based on metal-oxide-semiconductor transistor structures. A nonvolatile memory element may be based on a metal-oxide-semiconductor transistor structure that has a gate, a drain, a source, and a body. During pr... | 02/14/2012 |
| 8036027 | Semiconductor device and memory A memory applicable to an embedded memory is provided. The memory includes a substrate, a gate, a charge-trapping gate dielectric layer, a source, and a drain. The gate is disposed above the substrate. The charge-trapping gate dielectric layer is disposed between th... | 10/11/2011 |
| 8014195 | Single transistor memory cell A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and... | 09/06/2011 |
| 7978510 | Stochastic synapse memory element with spike-timing dependent plasticity (STDP) An active memory element is provided. A bipolar memory two-terminal element includes polarity-dependent switching. A probability of switching of the bi-polar memory element between a first state and a second state decays exponentially based on time delay and a diffe... | 07/12/2011 |
| 7940559 | Memory array having a programmable word length, and method of operating same A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistor... | 05/10/2011 |
| 7933148 | Memory A memory capable of suppressing reduction of data determination accuracy is provided. This memory includes a memory cell connected to a bit line for holding data and a bipolar transistor whose base is connected to the bit line. In data reading, the memory reads the ... | 04/26/2011 |
| 7843721 | Memory cell including an emitter follower and emitter follower sensing scheme and method of reading data therefrom A memory device including a static random access memory (SRAM) cell comprising junction field effect transistors (JFETs) has been disclosed. The memory cell includes a first bipolar junction transistor (BJT) for driving a bit line at logic levels having a potential ... | 11/30/2010 |
| 7733693 | Semiconductor memory device and method of operating same There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this ... | 06/08/2010 |
| 7679955 | Semiconductor switching device A switching device and methods of making and operating the same are provided. In one aspect, a method of operating a switching device is provided that includes providing a MOS transistor that has a gate, a source region, a drain region and a body region. A bipolar t... | 03/16/2010 |
| 7639528 | Nanocrystal write once read only memory for archival storage Structures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a first source/drain region, a se... | 12/29/2009 |
| 7606066 | Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same A technique of writing, programming, holding, maintaining, sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floa... | 10/20/2009 |
| 7593257 | Memory A memory capable of suppressing reduction of data determination accuracy is provided. This memory includes a memory cell connected to a bit line for holding data and a bipolar transistor whose base is connected to the bit line. In data reading, the memory reads the ... | 09/22/2009 |
| 7554839 | Symmetric blocking transient voltage suppressor (TVS) using bipolar transistor base snatch A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in ... | 06/30/2009 |
| 7539069 | Semiconductor memory device This disclosure concerns a memory comprising a memory cell; a first and a second sense nodes transmitting the data on the first and the second bit lines which transmits data with reversed polarities from each other; a first transfer gate provided between the first b... | 05/26/2009 |
| 7492632 | Memory array having a programmable word length, and method of operating same A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistor... | 02/17/2009 |
| 7477540 | Bipolar reading technique for a memory cell having an electrically floating body transistor A technique of sampling, sensing, reading and/or determining the data state of a memory cell (of, for example, a memory cell array) including an electrically floating body transistor. In this regard, the intrinsic bipolar transistor current component is employed to ... | 01/13/2009 |
| 7443722 | Semiconductor device and driving method therefor A semiconductor device includes a bulk semiconductor substrate, a plurality of storage elements, a bit line, a first voltage being applied to the first region side of the thyristor, and a voltage lower than the first voltage being applied to a word line. The plurali... | 10/28/2008 |
| 7415245 | Pulse shaping signals for ultrawideband communication An ultrawideband radio frequency pulse is generated by shaping a carrier signal having a selected frequency with a window function. The shaped carrier is gated to produce the ultrawideband pulse. In further embodiments, the window function comprises a sinusoidal fun... | 08/19/2008 |
| 7369450 | Nonvolatile memory having latching sense amplifier and method of operation A memory comprises a sense amplifier for sensing a logic state of a selected bitline. The sense amplifier includes a first precharge circuit, a current-to-voltage converter, a latch circuit, and a second precharge circuit. The first precharge circuit is for precharg... | 05/06/2008 |
| 7362609 | Memory cell A one-transistor (1T) NVRAM cell that utilizes silicon carbide (SiC) to provide both isolation of non equilibrium charge, and fast and non destructive charging/discharging. To enable sensing of controlled resistance (and many memory levels) rather than capacitance, ... | 04/22/2008 |
| 7348653 | Resistive memory cell, method for forming the same and resistive memory array using the same A resistive memory cell employs a photoimageable switchable material, which is patternable by actinic irradiation and is reversibly switchable between distinguishable resistance states, as a memory element. Thus, the photoimageable switchable material is directly pa... | 03/25/2008 |
| 7349273 | Access circuit and method for allowing external test voltage to be applied to isolated wells An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective well... | 03/25/2008 |
| 7335594 | Method for manufacturing a memory device having a nanocrystal charge storage region A method for manufacturing a memory device having a metal nanocrystal charge storage structure. A substrate is provided and a first layer of dielectric material is grown on the substrate. An absorption layer is formed on the first layer of dielectric material. The a... | 02/26/2008 |
| 7336530 | CMOS pixel with dual gate PMOS A pixel circuit with a dual gate PMOS is formed by forming two P+ regions in an N− well. The N− well is in a P− type substrate. The two P+ regions form the source and drain of a PMOS transistor. The PMOS t... | 02/26/2008 |
| 7335581 | Semiconductor memory device and method of manufacturing the same A method of manufacturing a semiconductor memory device includes the steps of providing a gate insulating film on an active region, depositing a first conductive film on the gate insulating film, processing the first conductive film, the gate insulating film, and th... | 02/26/2008 |
| 7332769 | Non-volatile memory arrangement having nanocrystals The amount of current flowing in the bitline during reading of a memory cell which is in the conductive state, hereinafter called the memory cell current, can be amplified manifold by changing the above mentioned select transistors to a novel device which is describ... | 02/19/2008 |
| 7327616 | Non-volatile semiconductor memory device The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit li... | 02/05/2008 |
| 7324366 | Non-volatile memory architecture employing bipolar programmable resistance storage elements A nonvolatile memory array includes a plurality of word lines, a plurality of bit lines, a plurality of source lines, and a plurality of nonvolatile memory cells. Each of at least a subset of the plurality of memory cells has a first terminal connected to one of the... | 01/29/2008 |
| 7324400 | Programming and evaluating through PMOS injection A PMOS transistor includes a gate, drain, and source in a substrate and is isolated from adjacent transistors in the substrate by shallow trench isolation. The transistor is programmed by applying a gate voltage to the gate and generating a drain-to-source voltage a... | 01/29/2008 |
| 7321143 | Ion-sensitive field effect transistor and method for producing an ion-sensitive field effect transistor An ion-sensitive field effect transistor includes a substrate on which there are formed a source region and a drain region. Above a channel region, the ion-sensitive field effect transistor has a gate with a sensitive layer including a metal oxide nitride mixture an... | 01/22/2008 |
| 7319058 | Fabrication method of a non-volatile memory A fabrication method for a non-volatile memory is provided. To fabricate the non-volatile memory, a plurality of first trenches and second trenches are formed in a substrate, wherein the second trenches are disposed above the first trenches and cross over the first ... | 01/15/2008 |
| 7319611 | Bitline transistor architecture for flash memory A memory array includes a buried diffusion region, a first source line that supplies electrical power to the buried diffusion region, a second source line that supplies electrical power to the buried diffusion region, a first bitline transistor having a first channe... | 01/15/2008 |
| 7315466 | Semiconductor memory device and method for arranging and manufacturing the same A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input ... | 01/01/2008 |
| 7309650 | Memory device having a nanocrystal charge storage region and method A memory device having a metal nanocrystal charge storage structure and a method for its manufacture. The memory device may be manufactured by forming a first oxide layer on the semiconductor substrate, then disposing a porous dielectric layer on the oxide layer and... | 12/18/2007 |
| 7310004 | Apparatus and method of interconnecting nanoscale programmable logic array clusters An apparatus and methods for interconnecting a plurality of nanoscale programmable logic array (PLA) clusters are disclosed. The appartus allows PLA clusters to be built at nanoscale dimensions, signal restoration to occur at the nanoscale, and interconnection betwe... | 12/18/2007 |
| 7310259 | Access circuit and method for allowing external test voltage to be applied to isolated wells An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective well... | 12/18/2007 |
| 7310266 | Semiconductor device having memory cells implemented with bipolar-transistor-antifuses operating in a first and second mode A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing inform... | 12/18/2007 |
