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| Number | Title | Issue Date |
| 8120951 | Memory devices, memory device constructions, constructions, memory device forming methods, current conducting devices, and memory cell programming methods Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the ... | 02/21/2012 |
| 8098521 | Method of providing an erase activation energy of a memory device A write-once read-many times memory device is made up of first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrode. The memory device is programmed by providing a charged species ... | 01/17/2012 |
| 8072801 | Method for creating nonequilibrium photodetectors with single carrier species barriers A method of forming a diode comprises the steps of forming an extraction region of a first conductivity type, forming an active region of a second conductivity type that is opposite the first conductivity type, and forming an exclusion region of the second conductiv... | 12/06/2011 |
| 7995384 | Electrically isolated gated diode nonvolatile memory A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Adjacent memory devices are electrically isolated. Example embodiments include the individual memory cell, an array of such memory cell... | 08/09/2011 |
| 7940558 | Integrated circuit comprising a thyristor and method of controlling a memory cell comprising a thyristor An integrated circuit is provided comprising an array of memory cells connected by word and bit lines, respectively, wherein each memory cell comprises a thyristor structure, an anode terminal that connects the thyristor structure with a respective bit line, a gate ... | 05/10/2011 |
| 7916529 | Pin diode device and architecture A memory architecture that employs one or more semiconductor PIN diodes is provided. The memory employs a substrate that includes a buried bit/word line and a PIN diode. The PIN diode includes a non-intrinsic semiconductor region, a portion of the bit/word line, and... | 03/29/2011 |
| 7916530 | SCR matrix storage device In various embodiments, an addressable storage matrix includes a first plurality of intersection points, at least some of which are bridged by two-terminal non-linear elements that exhibit a threshold below which current flow is significantly lower than if the thres... | 03/29/2011 |
| 7911833 | Anti-parallel diode structure and method of fabrication An anti-parallel diode structure and method of fabrication is presently disclosed. In some embodiments, an anti-parallel diode structure has a semiconductor region comprising a first insulator layer disposed between a first semiconductor layer and a second semicondu... | 03/22/2011 |
| 7768825 | Gated diode nonvolatile memory structure with diffusion barrier structure A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal and a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memo... | 08/03/2010 |
| 7746690 | Memory comprising diode A memory operable at a high speed is obtained. This memory comprises a plurality of word lines, first transistors each connected to each the plurality of word lines for entering an ON-state through selection of the corresponding word line, a plurality of memory cell... | 06/29/2010 |
| 7724567 | Memory device and method of refreshing A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltag... | 05/25/2010 |
| 7715229 | Memory device A memory device includes a memory unit comprising a substrate supporting mobile charge carriers. Insulative features formed on the substrate surface define first and second substrate areas on either side of the insulative features areas being connected by an elongat... | 05/11/2010 |
| 7672157 | Gated diode nonvolatile memory cell array A memory integrated circuit has memory arrays that are vertically layered. These memory arrays include word lines and bit lines. Intersections between the word lines and the bit lines include a diode and a memory state storage element. The diode and the memory stora... | 03/02/2010 |
| 7652916 | SCR matrix storage device One of the simplest forms of data storage devices is the diode array storage device. However, a problem with diode array storage devices is that as the size of the array increases, the number of non-addressed diodes connected between a given selected row or column o... | 01/26/2010 |
| 7593256 | Memory array with readout isolation Methods and apparatus for differentially measuring the bit state of a particular element in an array of passive nonlinear elements against the output of a reference generator. The reference generator may be, for example, a dummy row circuit, a dummy column circuit, ... | 09/22/2009 |
| 7548454 | Memory array with readout isolation Methods and apparatus for measuring the bit state of a particular element in an array of passive nonlinear elements that are insensitive to loading effects from external connections to the array. In one embodiment, a switching element is used to electrically isolate... | 06/16/2009 |
| 7548453 | Memory array with readout isolation Methods and apparatus for providing an array of passive nonlinear elements having an interface circuit that isolates the array from loading effects from external connections to the array. In one embodiment, a capacitive switching circuit is used to electrically isol... | 06/16/2009 |
| 7548455 | Multi-valued logic/memory cells and methods thereof A memory cell and method for making a memory cell in accordance with embodiments of the present invention includes two or more tunnel diodes, a loading system, and a driving system. The two or more tunnel diodes are coupled together, the loading system is coupled to... | 06/16/2009 |
| 7483296 | Memory device with unipolar and bipolar selectors A memory device is proposed. The memory device includes a plurality of memory cells, wherein each memory cell includes a storage element and a selector for selecting the corresponding storage element during a reading operation or a programming operation. The selecto... | 01/27/2009 |
| 7474558 | Gated diode nonvolatile memory cell array A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of... | 01/06/2009 |
| 7466586 | Diode-based capacitor memory and its applications Diode-based capacitor memory uses relatively small capacitor, and uses a diode as an access device instead of MOS transistor, wherein the diode has four terminals, the first terminal is connected to a word line, the second terminal is connected to the first plate of... | 12/16/2008 |
| 7450416 | Utilization of memory-diode which may have each of a plurality of different memory states The present invention is a method of undertaking a procedure on a memory-diode, wherein a memory-diode is provided which is programmable so as to have each of a plurality of different threshold voltages. A reading of the state of the memory-diode indicates the so de... | 11/11/2008 |
| 7447063 | Nonvolatile semiconductor memory device The nonvolatile semiconductor memory device according the this invention has a plurality of memory cells arranged in a matrix form and each having a floating gate; at least one first diode connected between drains of said plurality of memory cells and a ground termi... | 11/04/2008 |
| 7417887 | Phase change memory device and method of driving word line thereof A method and device for driving the word lines of a phase change memory device is provided. The method may include applying a first voltage level to non-selected word lines and a second voltage level to selected word lines during a normal operational mode, and placi... | 08/26/2008 |
| 7411810 | One-time programmable memory In the present invention, one-time programmable memory includes a diode as an access device and a capacitor as a storage device, the diode includes four terminals, wherein the first terminal is connected to a word line, the second terminal is connected to one plate ... | 08/12/2008 |
| 7405960 | Semiconductor memory device and method for biasing dummy line therefor A semiconductor memory device and a dummy line biasing method in which in the semiconductor memory device of a diode structure including a plurality of memory cells each having one variable resistance device and one diode device, the memory device includes a plurali... | 07/29/2008 |
| 7379317 | Method of programming, reading and erasing memory-diode in a memory-diode array A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, f... | 05/27/2008 |
| 7376008 | SCR matrix storage device One of the simplest forms of data storage devices is the diode array storage device. However, a problem with diode array storage devices is that as the size of the array increases, the number of non-addressed diodes connected between a given selected row or column o... | 05/20/2008 |
| 7372306 | Method and apparatus for stability control using fast excitation in circuits having elements with negative differential resistance A method and state stabilizer for enhancing computing functionality by using fast excitations are described. The state stabilizer includes a voltage source for producing fast excitations having an associated excitation amplitude. An electronic device having an assoc... | 05/13/2008 |
| 7372753 | Two-cycle sensing in a two-terminal memory array having leakage current A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected tra... | 05/13/2008 |
| 7366051 | Word line driver circuitry and methods for using the same Word line driver circuitry for selectively charging and discharging one or more word lines is provided. The driver circuitry uses a dual transistor topology, where a first transistor is driven by a signal, DOUT, and a second transistor is driven by a time-delayed co... | 04/29/2008 |
| 7362609 | Memory cell A one-transistor (1T) NVRAM cell that utilizes silicon carbide (SiC) to provide both isolation of non equilibrium charge, and fast and non destructive charging/discharging. To enable sensing of controlled resistance (and many memory levels) rather than capacitance, ... | 04/22/2008 |
| 7352610 | Volatile memory elements with soft error upset immunity for programmable logic device integrated circuits Memory elements are provided that are immune to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements have nonlinear high-impedance two-terminal elements that restrict the flow of discharge currents during a particle stri... | 04/01/2008 |
| 7352617 | Nano tube cell and memory device using the same A nano tube cell and a memory device using the same features a cross point cell using a capacitor and a PNPN nano tube switch to reduce the whole memory size. In the memory device, the unit nano tube cell comprising a capacitor and a PNPN nano tube switch which does... | 04/01/2008 |
| 7348653 | Resistive memory cell, method for forming the same and resistive memory array using the same A resistive memory cell employs a photoimageable switchable material, which is patternable by actinic irradiation and is reversibly switchable between distinguishable resistance states, as a memory element. Thus, the photoimageable switchable material is directly pa... | 03/25/2008 |
| 7349248 | Non-volatile memory A non-volatile memory cell includes an upper electrode; a lower electrode and a state-variable region, in which a conductive state changes only once. The state variable region is formed in a region between the upper electrode and the lower electrode. The state-varia... | 03/25/2008 |
| 7349245 | Non-volatile phase-change memory device and associated program-suspend-read operation A method of performing a program-suspend-read operation in a PRAM device comprises programming a write block comprising N unit program blocks in response to a program operation request, and suspending the program operation after programming M unit program blocks, wh... | 03/25/2008 |
| 7349273 | Access circuit and method for allowing external test voltage to be applied to isolated wells An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective well... | 03/25/2008 |
| 7342276 | Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme... | 03/11/2008 |
| 7339186 | IC chip with nanowires Arrangement of nanowires with PN junctions between bit lines and word lines are arranged as a ROM memory cell array. A number of the nanowires have dielectric regions and are present only as a dummy. The connections between word and bit lines may also exist as trans... | 03/04/2008 |
