"The wireless music box has no imaginable commercial value. Who would pay for a message sent to nobody in particular?"
David Sarnoff, American radio pioneer ; 1921
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 5325325 | Semiconductor memory device capable of initializing storage data An SRAM is provided wherein each memory cell has first and second storage nodes to be maintained at complementary potentials corresponding to storage data and first and second inverters provided in anti-parallel between the first storage node and the seco... | 06/28/1994 |
| 5311465 | Semiconductor memory device that uses a negative differential resistance A semiconductor memory device comprises a memory cell transistor that includes two active parts each including therein an emitter and a base and showing a negative differential resistance. The collector layer is shared commonly by the two active parts and... | 05/10/1994 |
| 5307311 | Microvibratory memory device A memory device whose media scanning is vibrationally (cyclic harmonic vibration) or inertially (one-time pulsed read/write) driven is provided, comprising a plurality of cantilevers (7, 7', 7"), attached at one end and capable of vibrating. On the opposi... | 04/26/1994 |
| 5299150 | Circuit for preventing false programming of anti-fuse elements A circuit for preventing false programming of unselected anti-fuses in an anti-fuse array includes a series impedance including a plurality of transistors which may be used for partial address selection connected between a source of programming voltage an... | 03/29/1994 |
| 5296752 | Current memory cell A current memory cell for sampling a current (I) at a current terminal (5) during a sample interval and for applying the current (I) to the current terminal (5) during a hold interval. A first switch (S1) connects a PMOS transistor (P1) as a diode during ... | 03/22/1994 |
| 5297089 | Balanced bit line pull up circuitry for random access memories A balancing circuit which may be used as part of a random access memory system for eliminating bit line offset, is disclosed. The balancing circuit contemplated by the invention is capable of supporting rapid memory accesses (such as reads when the memory... | 03/22/1994 |
| 5293335 | Ceramic thin film memory device A digital memory circuit for electronic applications. The circuit has at least one memory element connected in series with a load resistor. The digital memory circuit also includes a voltage supply and a data output terminal. The memory element in the dig... | 03/08/1994 |
| 5289408 | Memory apparatus using tunnel current techniques A scanning tunneling microscope memory apparatus comprises first and second integrated circuit (IC) substrates. First and second cantilevers, which can be moved by piezoelectric elements, are arranged on the first and second IC substrates, respectively. T... | 02/22/1994 |
| 5287303 | SCR type memory apparatus An SCR type memory apparatus which is short in access time, easy in setting current values upon reading and writing and easy in constructing a peripheral circuit with less power supply voltage limitation is described. The semiconductor memory apparatus co... | 02/15/1994 |
| 5276638 | Bipolar memory cell with isolated PNP load A bipolar memory array and memory cell. The memory cell has a pair of cross coupled NPN storage transistors and a pair of PNP load transistors. The collector of each of the load transistors is connected to one of the storage transistors. A base, common to... | 01/04/1994 |
| 5255225 | Semiconductor integrated circuit device and memory consisting of semiconductor integrated circuit A semiconductor integrated circuit device including a level conversion circuit in which the simplifying of the circuit and the increasing of the speed of operation have been attained is provided. A pair of complementary output signals amplified to a required s... | 10/19/1993 |
| 5253202 | Word line driver circuit for dynamic random access memories A wordline driver circuit for reading the contents of a Dynamic Random Access Memory (DRAM). The circuit is implemented in CMOS and is capable of pulling the wordlines to a negative potential with respect to the substrate, thereby decreasing the access ti... | 10/12/1993 |
| 5243557 | Bi-CMOS semiconductor integrated circuit Disclosed here in is a semiconductor integrated circuit comprising a substrate, a memory cell array having a plurality of memory cells arranged in rows and columns, a plurality of word lines, and a plurality of bit lines, and a plurality of word-line driv... | 09/07/1993 |
| 5235543 | Dual port static memory with one cycle read-modify-write A dual port static memory cell with one cycle read-modify-write operation. The static memory cell includes a write line for receiving new data to be written into the static memory cell, switching means for coupling the new data into the static memory cell... | 08/10/1993 |
| 5216631 | Microvibratory memory device A memory device whose media scanning is vibrationally (cyclic harmonic vibration) or inertially (one-time pulsed read/write) driven is provided, comprising a plurality of cantilevers (7, 7', 7"), attached at one end and capable of vibrating. On the opposi... | 06/01/1993 |
| 5216632 | Memory arrangement with a read-out circuit for a static memory cell A memory arrangement that includes a static memory cell with two MOSFETs that are connected such that an input signal for setting the memory cell is applied to one MOSFET, and the output of the other MOSFET is connected to the input of the first MOSFET, s... | 06/01/1993 |
| 5164916 | High-density double-sided multi-string memory module with resistor for insertion detection A high-density memory module has thirty-two memory integrated circuit chips, sixteen decoupling capacitors, and two resistors mounted on a double-sided multi-layer printed wiring board having a series of edge terminals for connection to a motherboard. One... | 11/17/1992 |
| 5162819 | Information processing apparatus, information processing method, and recording medium employed therefor An information processing apparatus comprises a recording medium having at least an underlying electrode and a photoconductive thin film and having an insulating or semiconducting recording region capable of accumulating an electric charge; and a probe el... | 11/10/1992 |
| 5144581 | Apparatus including atomic probes utilizing tunnel current to read, write and erase data A micro scanning tunneling microscope ("STM") arithmetic circuit device comprises an information-rewritable micro STM recording medium and a micro STM recording apparatus which temporarily stores information on the recording medium such that the informati... | 09/01/1992 |
| 5136533 | Sidewall capacitor DRAM cell A dynamic RAM is provided with enhanced charge storage capacity by increasing the surface area between the two electrodes of the storage capacitor. The first electrode consists of a thick conductive layer whose vertical sidewalls provide the extra surface... | 08/04/1992 |
| 5136534 | Method and apparatus for a filament channel pass gate ferroelectric capacitor memory cell A memory cell is disclosed which comprises a filament channel transistor and a ferroelectric capacitor formed on a surface of a semiconductor substrate. The transistor comprises a substantially cylindrical channel filament which is formed substantially pe... | 08/04/1992 |
| 5132934 | Method and apparatus for storing digital information in the form of stored charges Method and apparatus for storing digital information in a dense memory structure. A semiconductor substrate has a thin insulating layer formed thereon. Over the thin insulating layer is formed a dielectric charge-storage layer. A piezoelectric bimorph can... | 07/21/1992 |
| 5122986 | Two transistor dram cell A semiconductor memory cell includes a write row line, a read row line, a write column line, a read column line, a single MOS write transistor, and a single MOS read transistor. The write transistor has a first controlled node coupled to the write column ... | 06/16/1992 |
| 5121357 | Static random access split-emitter memory cell selection arrangement using bit line precharge This invention relates generally to the static, random access, semiconductor memory arrays which incorporate split-emitter memory cells. The latter are accessed during a read cycle of a selected memory cell by precharging all the bit lines of unselected m... | 06/09/1992 |
| 5119163 | Semiconductor device A semiconductor device includes memory cells each of which include a plurality of groups of an anti-fuse and a transistor connected in series; a capacitor including first and second electrodes, with the first electrode connected to a bit line of the memor... | 06/02/1992 |
| 5084838 | Large-scale integrated circuit device such as a wafer scale memory having improved arrangements for bypassing, redundancy, and unit integrated circuit interconnection A plurality of unit integrated circuits mounted on a large-scale integrated circuit device, for example, a wafer scale memory, are each provided with a bypass circuit which selectively shorts input and output nodes in the corresponding unit integrated cir... | 01/28/1992 |
| 5077688 | Semiconductor memory device having improved memory cells provided with cylindrical type capacitors A semiconductor memory device having a storage region constituted with the arrangement of a plurality of memory cells on a main surface of a semiconductor substrate. Each memory cell includes a switching element and a passive element for signal retention ... | 12/31/1991 |
| 5077687 | Gallium arsenide addressable memory cell An addressable memory cell (10) which is composed of an interrupt transistor (20) of the field-effect type whose source (S) is connected to the input terminal (I) of the cell (10) and whose gate (G) is connected to a clock (H, H) and a loop (30) which inc... | 12/31/1991 |
| 5036490 | Memory device with dual cantilever means The memory device comprises a recording member in which perturbations are selectively formed, a probe for detecting the presence or absence of the perturbations, a first cantilever having the recording member at a forward end, and a second cantilever havi... | 07/30/1991 |
| 5023836 | Semiconductor memory device A semiconductor memory device comprises a transistor and a resistor. The transistor has negative differential resistance characteristics in an emitter current or a source current thereof. Therefore the semiconductor memory device has few elements and a si... | 06/11/1991 |
| 5023835 | Semiconductor memory system for use in logic LSI's A semiconductor memory system includes a memory section formed on a semiconductor substrate and having decode means for decoding an address signal, and a logic section formed on the semiconductor substrate and having address signal forming means for formi... | 06/11/1991 |
| 5020027 | Memory cell with active write load A memory cell responsive to a write enable signal for storing write signals present on a pair of write bit lines and responsive to a read enable signal for presenting stored data on a pair of read sense lines further includes a timed, active write load. T... | 05/28/1991 |
| 4991136 | Semiconductor associative memory device with memory refresh during match and read operations A semiconductor associative memory device comprises a content addressable memory cell connected to a word line, a bit line, an inversion bit line and a match line. The memory cell comprises first and second n channel MOS transistors constituting a capacit... | 02/05/1991 |
| 4970685 | Semiconductor memory device having a divided bit line structure A semiconductor memory device includes an array of memory cells arranged in rows and columns, a plurality of divided bit line pairs connecting the memory cells, the divided bit line pairs extending along a given column of memory cells, and a pair of main ... | 11/13/1990 |
| 4970689 | Charge amplifying trench memory cell A gain memory cell circuit includes a storage capacitor connected between a storage node and ground, a write word line, a read word line, a second capacitor capactively coupling the read word line to the storage node, a read transistor having its source/d... | 11/13/1990 |
| 4958320 | Radiation resistant bipolar memory A bipolar memory of a construction having high immunity to soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuitry of the memory cell, are inverted and the load device thereof has shielding means fo... | 09/18/1990 |
| 4958318 | Sidewall capacitor DRAM cell A dynamic RAM is provided with enhanced charge storage capacity by increasing the surface area between the two electrodes of the storage capacitor. The first electrode consists of a thick conductive layer whose vertical sidewalls provide the extra surface... | 09/18/1990 |
| 4945515 | Memory writing apparatus An input section comprising a needle which has a fine tip portion. A data is written in a memory by applying electrical stimulation between the tip portion of the needle and the memory. A memory writing apparatus enables non-contact recording on an atomic... | 07/31/1990 |
| 4943740 | Ultra fast logic The logic has an extremely high speed, very low number of components and large common mode rejection, and is intended to eliminate the emitter-coupled logic (ECL). The supply voltage and power consumption are small. The logic is particularly for digital s... | 07/24/1990 |
| 4942555 | Bi-MOS semiconductor memory having high soft error immunity A semiconductor memory is provided having high reliability, and which particularly prevents data destruction by rays, and the like. In a semiconductor memory for detecting memory data from the conduction ratio between a transistor of a flip-flop type memo... | 07/17/1990 |