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| Number | Title | Issue Date |
| 7193893 | Write once read only memory employing floating gates Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate tra... | 03/20/2007 |
| 7190607 | Phase-change memory element driver circuits using measurement to control current and methods of controlling drive current of phase-change memory elements using measurement Programming phase-change memory devices and driver circuits for programming phase-change memory devices are provided that control an amount of current supplied to a phase-change material of the phase-change memory device based on a measure of resistance of the phase... | 03/13/2007 |
| 7109532 | High Ion/Ioff SOI MOSFET using body voltage control A semiconductor device may comprise a partially-depleted SOI MOSFET having a floating body region disposed between a source and drain. The floating body region may be driven to receive injected carriers for adjusting its potential during operation of the MOSFET. In ... | 09/19/2006 |
| 7105900 | Reduced floating body effect static random access memory cells and methods for fabricating the same An SRAM cell that may reduce or eliminate floating body effect when using a SOI and a method for fabricating the same are provided. A floating body of an access transistor of the SRAM is connected to a source region of a driver transistor, for example, through a bod... | 09/12/2006 |
| 6939175 | Coaxial cable for overvoltage protection A coaxial cable for transmitting high frequency signals includes includes a body having a center conductor and a shield formed coaxially around the center conductor and separated from the center conductor by a layer of dielectric having an annular layer of electro-s... | 09/06/2005 |
| 6826712 | Memory device having redundant cells According to an aspect of the present invention, a redundant file memory for recording first replacement information having an address of a defective cell to be replaced with a redundant cell is configured by a memory cell having the same configuration as an ordinar... | 11/30/2004 |
| 6599796 | Apparatus and fabrication process to reduce crosstalk in pirm memory array A cross point memory array is fabricated on a substrate with a plurality of memory cells, each memory cell including a diode and an anti-fuse in series. First and second conducting materials are disposed in separate strips on the substrate to form a plura... | 07/29/2003 |
| 6549450 | Method and system for improving the performance on SOI memory arrays in an SRAM architecture system The present invention provides an SOI SRAM architecture system which holds all the bitlines at a lower voltage level, for example, ground, or a fraction of Vdd, during array idle or sleep mode. Preferably, the bitlines are held at a voltage level approxim... | 04/15/2003 |
| 5943258 | Memory with storage cells having SOI drive and access transistors with tied floating body connections An integrated circuit (10). The integrated circuit comprises a first SOI transistor (AT3) having a body and for performing first function. The integrated circuit further comprises a second SOI transistor (DT3) having a body and for performing a second fun... | 08/24/1999 |
