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Pizza Pie With Concentric Rings of Crust
A pizza mold for forming a plurality of concentric raised ridges of dough (i.e., crust) on the surface of a pizza pie.
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| Number | Title | Issue Date |
| 8270209 | Josephson magnetic random access memory system and method One aspect of the present invention includes a Josephson magnetic random access memory (JMRAM) system. The system includes an array of memory cells arranged in rows and columns. Each of the memory cells includes an HMJJD that is configured to store a digital state c... | 09/18/2012 |
| 7443720 | Method and circuit for reading quantum state A single electron-transistor is used to read out charge states of two coupled qubits formed by two Cooper pair boxes. Detection is made about a gate voltage shift of the peak of the current that flows in the single electron transistor in accordance with the charge s... | 10/28/2008 |
| 7382678 | Delay stage-interweaved analog DLL/PLL A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized de... | 06/03/2008 |
| 7323711 | High-temperature superconductive device A high-temperature superconductive device is disclosed, including a ramp-edge junction. The ramp-edge junction includes a first electrode layer (5) that defines the size of the ramp-edge junction and a second electrode layer (6). The width of the secon... | 01/29/2008 |
| 7268713 | Superconducting circuit A circuit includes a latch circuit including a Josephson junction and configured to perform a latch operation based on a hysteresis characteristic in response to a single flux quantum, a load circuit including load inductance and load resistance and coupled to an ou... | 09/11/2007 |
| 7268576 | Superconducting qubit with a plurality of capacitive couplings A first qubit having a superconducting loop interrupted by a plurality of Josephson junctions is provided. Each junction interrupts a different portion of the superconducting loop and each different adjacent pair of junctions in the plurality of Josephson junctions ... | 09/11/2007 |
| 7253654 | Superconducting qubits having a plurality of capacitive couplings A first qubit having a superconducting loop interrupted by a plurality of Josephson junctions is provided. Each junction interrupts a different portion of the superconducting loop and each different adjacent pair of junctions in the plurality of Josephson junctions ... | 08/07/2007 |
| 7230415 | Quantum junction device as switch and detector A quantum junction device having three or more wires connected to a loop surrounding a magnetic flux is used to act as a switch responsive to magnetic flux and therefore useable for mass storage devices or as a flux detector by sensing current direction, conductance... | 06/12/2007 |
| 7203794 | Destructive-read random access memory system buffered with destructive-read memory cache A memory storage system includes a plurality of memory storage banks and a cache in communication therewith. Both the plurality of memory storage banks and the cache further include destructive read memory storage elements configured for delayed write back schedulin... | 04/10/2007 |
| 7177180 | Method and apparatus for reading data from a ferromagnetic memory cell A ferromagnetic memory cell is disclosed. The cell includes a bit (10), made of a ferromagnetic material, having a remnant polarity. The cell also includes a read drive line (20) coupled to a first portion of the bit (10), to feed a current into... | 02/13/2007 |
| 7135701 | Adiabatic quantum computation with superconducting qubits A method for computing using a quantum system comprising a plurality of superconducting qubits is provided. Quantum system can be in any one of at least two configurations including (i) an initialization Hamiltonian H0 and (ii) a problem Hamiltonian H | 11/14/2006 |
| 7129870 | Superconducting latch driver circuit generating sufficient output voltage and pulse-width A circuit includes a latch circuit including a Josephson junction and configured to perform a latch operation based on a hysteresis characteristic in response to a single flux quantum, a load circuit including load inductance and load resistance and coupled to an ou... | 10/31/2006 |
| 7123500 | 1P1N 2T gain cell A two-transistor DRAM cell includes an NMOS device and a PMOS device coupled to the NMOS device. ... | 10/17/2006 |
| 6979836 | Superconducting low inductance qubit A superconducting structure that can operate, for example, as a qubit or a superconducting switch is presented. The structure includes a loop formed from two parts. A first part includes two superconducting materials separated by a junction. The junction can, for ex... | 12/27/2005 |
| 6975534 | Thin film magnetic memory device having a highly integrated memory array Read word lines and write word lines are provided corresponding to the respective MTJ (Magnetic Tunnel Junction) memory cell rows, and bit lines and reference voltage lines are provided corresponding to the respective MTJ memory cell columns. Adjacent MTJ memory cel... | 12/13/2005 |
| 6960929 | Superconductive crossbar switch A superconductor crossbar switch for connecting a plurality of inputs with a plurality of outputs, including a switching cell having an input, an output and a circuit for connecting the input with the output for bidirectionally transmitting data therebetween. The co... | 11/01/2005 |
| 6949402 | Method of forming a non-volatile resistance variable device A method of metal doping a chalcogenide material includes forming a metal over a substrate. A chalcogenide material is formed on the metal. Irradiating is conducted through the chalcogenide material to the metal effective to break a chalcogenide bond of the chalcoge... | 09/27/2005 |
| 6948028 | Destructive-read random access memory system buffered with destructive-read memory cache A memory storage system is disclosed. In an exemplary embodiment, the memory storage system includes a plurality of memory storage banks and a cache in communication therewith. Both the plurality of memory storage banks and the cache further include destructive read... | 09/20/2005 |
| 6943368 | Quantum logic using three energy levels A method for quantum computing with a quantum system comprising a first energy level, a second energy level, and a third energy level. The first energy level and said second energy level are capable of being degenerate with respect to each other. In the method a sig... | 09/13/2005 |
| 6916719 | Method and apparatus for non-conductively interconnecting integrated circuits Methods and apparatus are described for capacitively signaling between different semiconductor chips and modules without the use of connectors, solder bumps, wire-bond interconnections or the like. Preferably, pairs of half-capacitor plates, one half located on each... | 07/12/2005 |
| 6847546 | High-sensitivity magnetic field sensor There is provided a high sensitive magnetic field sensor which has a Josephson junction section (2) using a bismuth 2212 oxide high-temperature superconductor single-crystal (1) and is operated based on a periodical variation in a Josephson vortex flow... | 01/25/2005 |
| 6836141 | Superconductor ballistic RAM A superconductor memory array (10) has a high associated throughput with low power dissipation and a simple architecture. The superconductor memory array (10) includes memory cells (12a-12d) arranged in a row-column format a... | 12/28/2004 |
| 6803599 | Quantum processing system for a superconducting phase qubit A control system for an array of qubits is disclosed. The control system according to the present invention provides currents and voltages to qubits in the array of qubits in order to perform functions on the qubit. The functions that the control system can perform ... | 10/12/2004 |
| 6734454 | Internally shunted Josephson junction device A Josephson junction has inherent resistance which effectively shunts the junction and thereby obviates a separate shunt resistor and thus reduces surface area in an integrated circuit including a plurality of Josephson junctions. The Josephson junction comprises a ... | 05/11/2004 |
| 6728131 | Fluxon injection into annular Josephson junctions A method for inserting fluxons into an annular Josephson junction is disclosed. Fluxon injection according to the present invention is based on local current injection into one of the superconducting electrodes of the junction. By choosing an appropriate value for t... | 04/27/2004 |
| 6452831 | Single electron resistor memory device and method A memory device includes a plurality of cells, each having a first electrode coupled to a first location on semiconductor material, a second electrode coupled to a second location disposed away from the first location on the semiconductor material and a p... | 09/17/2002 |
| 6242939 | Superconducting circuit having superconductive circuit device of voltage-type logic and superconductive circuit device of fluxoid-type logic device selectively used therein A superconducting circuit device of a voltage-type logic device is large in current driving capability and, accordingly, electric power consumption; however, the switching speed is not so fast, and a superconducting circuit device of a fluxoid-type logic ... | 06/05/2001 |
| 6229332 | Superconductive logic gate and random access memory The present invention is a superconductive logic gate assembly (50, 100), a superconductive NOR gate assembly (10), and a superconductive random access memory (150). A superconductive logic gate assembly in accordance with the invention includes a plurali... | 05/08/2001 |
| 6060664 | Electronic circuit component A prior-art electronic circuit component comprising an insulating film and a circuit conductive layer made of a superconducting metal suffers low reliability resulting from insufficient adhesion between these layers. An electronic circuit component of the... | 05/09/2000 |
| 5942765 | High-temperature superconducting random access memory In the random access memory utilizing an oxide high-temperature superconductor, a first high-temperature superconductor layer 1, a non-superconductor layer 2, a second high-temperature superconductor layer 3 and a non-superconductor layer 4 are formed on ... | 08/24/1999 |
| 5930165 | Fringe field superconducting system The instant invention is a switch, comprising: (1) a pathway of a superconductive material; and (2) a ferromagnet, where the ferromagnet is adapted for having at least a first magnetization state and a second magnetization state, where fringe fields from ... | 07/27/1999 |
| 5872731 | Multi-state Josephson memory A multi-state Josephson memory in a superconductor integrated circuit includes a plurality of superconductive quantum interference device (SQUID) memory cells 2 each having a SQUID 4 characterized by a SQUID loop inductance L and a junction critical curre... | 02/16/1999 |
| 5831278 | Three-terminal devices with wide Josephson junctions and asymmetric control lines A three-terminal device constructed from a Josephson junction with one or more asymmetric control lines is disclosed. The device is constructed with high temperature superconducting materials. The junction can be a bicrystal, SNS (Superconducting-Normal-S... | 11/03/1998 |
| 5629889 | Superconducting fault-tolerant programmable memory cell incorporating Josephson junctions A superconducting fault-tolerant programmable read-only memory (SFT-PROM) cell stores information in the phases of superconducting wires in a Josephson array. The information is addressable and retrievable in a fault-tolerant manner due to the non local n... | 05/13/1997 |
| 5610857 | Memory element with multibit storage A memory element for multiple bit storage uses a plurality of Josephson junction devices coupled in parallel between a ground plane and a superconductive line. A gate current is directly coupled to the superconductive line at a midpoint, and a control cur... | 03/11/1997 |
| 5442195 | Superconducting device including plural superconducting electrodes formed on a normal conductor A superconducting device may include a superconducting weak link equipped with plural superconducting devices that are used as input-output terminals formed on the same plane and at least one current source for applying current to at least one of these su... | 08/15/1995 |
| 5434530 | Superconducting semiconducting cross-bar circuit A hybrid superconducting-semiconducting field effect transistor-like circuit element comprised of a superconducting field effect transistor and a closely associated cryogenic semiconductor inverter for providing signal gain is described. The hybrid circui... | 07/18/1995 |
| 5388068 | Superconductor-semiconductor hybrid memory circuits with superconducting three-terminal switching devices Superconducting-semiconducting hybrid memories are disclosed. These superconducting-semiconducting hybrid memories utilize semiconductor circuits to store information, and either superconducting or semiconducting or combinations of superconducting and sem... | 02/07/1995 |
| 5377141 | Superconducting magnetic memory device having intentionally induced non-superconducting regions A new type of superconducting memory is described. The composition of superconducting ceramic material used in the memory has been altered in order to expedite the formation of non-superconducting regions formed of grain boundaries. Non-superconducting re... | 12/27/1994 |
| 5365476 | Three-port Josephson memory cell for superconducting digital computer A three-port Josephson memory cell has one input port (a data line) and two output ports (first and second sense lines). The memory cell receives a write enable pulse on a write line to store a bit of data from the data line as circulating supercurrent. T... | 11/15/1994 |
