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| Number | Title | Issue Date |
| 7995380 | Negative differential resistance pull up element for DRAM A memory cell includes a pull-up element that exhibits a refresh behavior that is dependent on the data value stored in the memory cell. The pull-up element is an NDR FET connected between a high voltage source and a storage node of the memory cell. The NDR FET rece... | 08/09/2011 |
| 7961505 | Electronic device, method of manufacturing the same, and storage device An electronic device includes: a first conductor; an insulative supporting film formed in a part on one surface of the first conductor; and a second conductor, one surface of which is opposed to the one surface of the first conductor and a part of which is supported... | 06/14/2011 |
| 7724587 | Apparatuses, computer program products and methods for reading data from memory cells In reading data from a memory cell, a determining circuit determines whether a received voltage value is within at least one first voltage range through a one-time read operation using a semiconductor device that senses an output current corresponding to the receive... | 05/25/2010 |
| 7577022 | Electric element, memory device, and semiconductor integrated circuit formed using a state-variable material whose resistance value varies according to an applied pulse voltage An electric element includes: a first electrode (1); a second electrode (3); and a layer (2) connected between the first electrode and the second electrode and having a diode characteristic and a variable resistance characteristic. The layer ( | 08/18/2009 |
| 7508701 | Negative differential resistance devices and approaches therefor Negative differential resistance devices are implemented to facilitate current flow under different operating conditions. According to an example embodiment of the present invention, an NDR device is arranged for selective passage of current through relatively high ... | 03/24/2009 |
| 7505309 | Static RAM memory cell with DNR chalcogenide devices and method of forming An SRAM memory device having improved stability including two series connected devices, at least one of the devices being a chalcogenide device exhibiting differential negative resistance characteristics. One of the two devices serves as the load of the other. A swi... | 03/17/2009 |
| 7440310 | Memory cell with trenched gated thyristor One aspect of this disclosure relates to a method for operating a memory cell. According to various embodiments, the method includes charging a storage node of the memory cell, including forward biasing a thyristor to switch the thyristor into a high conductance low... | 10/21/2008 |
| 7405963 | Dynamic data restore in thyristor-based memory device A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the... | 07/29/2008 |
| 7335965 | Packaging of electronic chips with air-bridge structures A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A circuit assembly comprises an electronic chip and a conductive structur... | 02/26/2008 |
| 7336523 | Memory device using nanotube cells A memory device using a nanotube cell comprises a plurality of nanotube sub-cell arrays each having a hierarchical bit line structure including a main bit line and a sub-bit line. In the memory device, a nanotube cell array comprising a capacitor and a PNPN nanotube... | 02/26/2008 |
| 7321507 | Reference cell scheme for MRAM An MRAM reference cell sub-array provides a mid-point reference current to sense amplifiers. The MRAM reference cell sub-array has MRAM cells arranged in rows and columns. Bit lines are associated with each column of the sub-array. A coupling connects the bit lines ... | 01/22/2008 |
| 7319254 | Semiconductor memory device having resistor and method of fabricating the same A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A stor... | 01/15/2008 |
| 7294527 | Method of forming a memory cell The invention relates to the fabrication of a resistance variable material cell or programmable metallization cell. The processes described herein can form a metal-rich metal chalcogenide, such as, for example, silver-rich silver selenide. Advantageously, the proces... | 11/13/2007 |
| 7292500 | Reducing read data strobe latency in a memory system A read activity detector circuit for use in a random access memory array includes a plurality of synchronizer circuits operative to receive a plurality of respective reference clock signals having a frequency that is substantially the same as a core reference clock ... | 11/06/2007 |
| 7283381 | System and methods for addressing a matrix incorporating virtual columns and addressing layers A system and methods for addressing unique locations in a matrix. According to some embodiments, the system includes a plurality of uniquely addressable locations. A plurality of virtual columns that include a plurality of serially connected switch elements provide ... | 10/16/2007 |
| 7283403 | Memory device and method for simultaneously programming and/or reading memory cells on different levels A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus ... | 10/16/2007 |
| 7245525 | Data restore in thryistor based memory devices In a thyristor based memory cell, one end of a reversed-biased diode is connected to the cathode of the thyristor. During standby, the second end of the diode is biased at a voltage that is higher than that at the cathode of the thyristor. During restore operation, ... | 07/17/2007 |
| 7237172 | Error detection and correction in a CAM An error detection and correction circuit is connected to at least one memory bank of a CAM device. During background processing (i.e., when the CAM is not performing reading, writing or searching functions) the error detection and correction circuit tests all of th... | 06/26/2007 |
| 7224002 | Silicon on insulator read-write non-volatile memory comprising lateral thyristor and trapping layer Disclosed herein is an improved thyristor-based memory cell. In one embodiment, the cell is formed in a floating substrate using Silicon-On-Insulator (SOI) technology. The cell preferably incorporates a lateral thyristor formed entirely in the floating substrate, an... | 05/29/2007 |
| 7220636 | Process for controlling performance characteristics of a negative differential resistance (NDR) device A variety of processes are disclosed for controlling NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters. The processes are based on conventional semiconductor manufacturing operation... | 05/22/2007 |
| 7186621 | Method of forming a negative differential resistance device A negative differential resistance (NDR) field-effect transistor element is disclosed, formed on a silicon-based substrate using conventional MOS manufacturing operations. Methods for improving a variety of NDR characteristics for an NDR element, such as peak-to-val... | 03/06/2007 |
| 7184295 | Memory device A memory device is provided in which recording of multi-valued data can be performed at a high speed and the recording of multi-valued data can be performed with a drive circuit having comparatively simple configuration. The memory device is formed of a memor... | 02/27/2007 |
| 7174351 | Method for deleting stored digital data from write-once memory device A digital storage system is coupled to a write-once memory array. File delete commands are implemented by over-writing a destructive digital pattern to at least a portion of the memory cells associated with the file to be deleted. One disclosed system alters the man... | 02/06/2007 |
| 7151292 | Dielectric memory cell structure with counter doped channel region A charge trapping dielectric memory cell array comprises a plurality of parallel bit lines implanted within the lightly doped substrate. The parallel bit lines define a plurality of channel regions spaced there between and form a semiconductor junction there with. A... | 12/19/2006 |
| 7123500 | 1P1N 2T gain cell A two-transistor DRAM cell includes an NMOS device and a PMOS device coupled to the NMOS device. ... | 10/17/2006 |
| 7123508 | Reference cells for TCCT based memory cells A reference cell produces a reference current that is about half of the current produced by a memory cell. The reference cell is essentially the same as the memory cell with an additional current reduction device that can be a transistor. Adjusting a reference volta... | 10/17/2006 |
| 7113423 | Method of forming a negative differential resistance device A negative differential resistance (NDR) field-effect transistor element is disclosed, formed on a silicon-based substrate using conventional MOS manufacturing operations. Methods for improving a variety of NDR characteristics for an NDR element, such as peak-to-val... | 09/26/2006 |
| 7095659 | Variable voltage supply bias and methods for negative differential resistance (NDR) based memory device Static random access memory (SRAM) performance is enhanced through the use of appropriate latch strength control. For example, latch strength in an SRAM cell is increased during data store operations to reduce power dissipation and improve reliability. Latch strengt... | 08/22/2006 |
| 7087919 | Layered resistance variable memory device and method of fabrication The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to one embodiment of the invention, a resistance variable memory element is provided having at ... | 08/08/2006 |
| 7071565 | Patterning three dimensional structures A three dimensional circuit structure including tapered pillars between first and second signal lines. An apparatus including a first plurality of spaced apart coplanar conductors disposed in a first plane over a substrate; a second plurality of spaced apart coplana... | 07/04/2006 |
| 7064977 | Reference cells for TCCT based memory cells A reference cell produces a reference current that is about half of the current produced by a memory cell. The reference cell is essentially the same as the memory cell with an additional current reduction device that can be a transistor. Adjusting a reference volta... | 06/20/2006 |
| 7057867 | Electrostatic discharge (ESD) protection clamp circuitry Electrostatic discharge (ESD) protection clamp circuitry including current tunneling circuitry to provide control current for controlling current shunting circuitry for shunting ESD current from the protected signal terminal. ... | 06/06/2006 |
| 7054191 | Method and system for writing data to memory cells A first and a second set of memory cells are connected to the same first word line and second word line. At the commencement of data writing, the first word line is set up. The first set of memory cells is read and temporarily stored into a buffer. At about the same... | 05/30/2006 |
| 7050327 | Differential negative resistance memory The invention relates to a DNR (differential negative resistance) exhibiting device that can be programmed to store information as readable current amplitudes and to methods of making such a device. The stored data is semi-volatile. Generally, information written to... | 05/23/2006 |
| 7042759 | Dynamic data restore in thyristor-based memory device A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the... | 05/09/2006 |
| 7026642 | Vertical tunneling transistor The disclosed embodiments relate to a vertical tunneling transistor that may include a channel disposed on a substrate. A quantum dot may be disposed so that an axis through the channel and the quantum dot is substantially perpendicular to the substrate. A gate may ... | 04/11/2006 |
| 7019342 | Double-gated transistor circuit An OR gate circuit includes double-gated four terminal transistor with independent gate control. First and second inputs are independently coupled to the top and bottom gates of the transistor. The drain is coupled to an output and precharged to a low voltage. An in... | 03/28/2006 |
| 7016224 | Two terminal silicon based negative differential resistance device A two terminal, silicon based negative differential resistance (NDR) element is disclosed, to effectuate a type of NDR diode for selected applications. The two terminal device is based on a three terminal NDR-capable FET which has a modified channel doping profile, ... | 03/21/2006 |
| 7012833 | Integrated circuit having negative differential resistance (NDR) devices with varied peak-to-valley ratios (PVRs) An integrated circuit is disclosed which includes a variety of NDR devices having different characteristics. The different NDR devices are formed to have different PVRs, different onset NDR voltages, etc. in a common substrate, by controlling various conventional pr... | 03/14/2006 |
| 7009208 | Memory device and method of production and method of use of same and semiconductor device and method of production of same A memory device able to be produced without requiring high precision alignment, a method of production of the same, and a method of use of a memory device produced in this way, wherein a peripheral circuit portion (first semiconductor portion) formed by a first mini... | 03/07/2006 |
