Quotables
"Without question, the greatest invention in the history of mankind is beer. Oh, I grant you that the wheel was also a fine invention, but the wheel does not go nearly as well with pizza."
Dave Barry
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8437179 | Semiconductor integrated circuit device with reduced leakage current The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage cur... | 05/07/2013 |
| 8437178 | Static random access memory cell and method of operating the same A static random access memory cell includes a latch unit. The latch unit includes a bi-inverting circuit and a switching circuit. The bi-inverting circuit has a first terminal and a second terminal. The switching circuit is electrically connected between the first t... | 05/07/2013 |
| 8411492 | Memory base cell and memory bank A memory base cell stores a bit of information implemented from a regular and compact structure made up of multiple identical and replicated base elements, on the “sea of gates” model, in which the base element of the structure is a cell able to be configured wi... | 04/02/2013 |
| 8400821 | Semiconductor storage device According to one embodiment, a dummy cell simulates an operation of a memory cell. A main dummy bit line transmits a signal read out from the dummy cell. An inverter makes a sense amplifier circuit to operate based on a potential of the main dummy bit line. n (n is ... | 03/19/2013 |
| 8379435 | Smart well assisted SRAM read and write An integrated circuit containing an array of SRAM cells with NMOS drivers and passgates, and an n-well bias control circuit which biases n-wells in each SRAM column independently. An integrated circuit containing an array of SRAM cells with PMOS drivers and passgate... | 02/19/2013 |
| 8379436 | Semiconductor memory device According to one embodiment, a semiconductor memory device includes a plurality of memory cells each of which is arranged at the intersection position between a pair of complementary bit lines and a word line, and stores data between a first power supply voltage app... | 02/19/2013 |
| 8363456 | Semiconductor device To improve reliability of a semiconductor device having an SRAM. The semiconductor device has a memory cell including six n-channel type transistors and two p-channel type transistors formed over a silicon substrate. Over the silicon substrate, a first p well... | 01/29/2013 |
| 8363455 | Eight transistor soft error robust storage cell A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes. The outer storage nodes act to limit feedback between the core storage nodes and are capable of res... | 01/29/2013 |
| 8351248 | CMOS SRAM memory cell with improved N/P current ratio A memory cell in an integrated circuit has a first PMOS transistor formed in N-type semiconductor material and a first NMOS transistor formed in P-type semiconductor material. A well bias line coupled to the N-type semiconductor material or to the P-type semiconduct... | 01/08/2013 |
| 8345470 | Semiconductor memory device A control circuit supplies a word line drive voltage to one of m word lines which corresponds to a memory cell to which data is to be written, during a word line drive period including a first period and a second period following the first period, to decrease curren... | 01/01/2013 |
| 8305798 | Memory cell with equalization write assist in solid-state memory A solid-state memory in which write assist circuitry is implemented within each memory cell. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and an equalization gate connected between the storage nodes of the storage element. ... | 11/06/2012 |
| 8289755 | Volatile memory elements with soft error upset immunity Memory elements are provided that exhibit immunity to soft error upsets. The memory elements may have cross-coupled inverters. The inverters may be implemented using programmable Schmitt triggers. The memory elements may be locked and unlocked by providing appropria... | 10/16/2012 |
| 8264862 | Low power SRAM based content addressable memory An apparatus comprising a memory array and a plurality of processing circuits. The memory array may be configured to store a plurality of data bits in a plurality of rows and a plurality of columns. A plurality of data words may be stored in a respective plurality o... | 09/11/2012 |
| 8243501 | SRAM device An SRAM device uses a four-terminal double gate field effect transistor as a selection transistor, wherein the four-terminal double gate field effect transistor comprises a gate which drives the transistor and a gate which controls a threshold voltage, which are ele... | 08/14/2012 |
| 8233302 | Content addressable memory with concurrent read and search/compare operations at the same memory cell A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match res... | 07/31/2012 |
| 8218354 | SRAM word-line coupling noise restriction A DC mode word-line coupling noise restriction circuit for multiple-port Random Access Memory cells. This circuit may comprise a Static Random Access Memory array. The SRAM array contains a plurality of columns and a plurality of rows with an SRAM cell formed at a c... | 07/10/2012 |
| 8218353 | Memory element circuitry with stressed transistors Integrated circuits with memory elements are provided. The memory elements may be arranged in a memory block. The memory block may include cross-coupled inverters that store data. The stored data may be used to program pass transistors. Transistors in the memory blo... | 07/10/2012 |
| 8213219 | Transistor-based memory cell and related operating methods A loadless static random access memory cell is provided. The memory cell includes four transistors. The first transistor has a gate terminal corresponding to a word line of the memory cell, a source/drain terminal corresponding to a first bit line of the memory cell... | 07/03/2012 |
| 8199560 | Memory device comprising select gate including carbon allotrope One or more embodiments relate to a memory device, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a control gate disposed over a charge storage layer; and a spacer select gate disposed over the substrate and laterally di... | 06/12/2012 |
| 8184475 | Robust local bit select circuitry to overcome timing mismatch An integrated circuit can include an SRAM array having cells arranged in columns, each column being connected to true and complementary read local bitlines RLBLT and RLBLC. A local bit-select circuit can be connected to the cells of a column of the SRAM array, which... | 05/22/2012 |
| 8164945 | 8T SRAM cell with two single sided ports A dual port SRAM cell includes an auxiliary driver transistor on each data node. The SRAM cell is capable of single sided write to each data node. The auxiliary driver transistors in addressed cells may be biased independently of half-addressed cells. During write a... | 04/24/2012 |
| 8159863 | 6T SRAM cell with single sided write An SRAM cell containing an auxiliary driver transistor is configured for a single sided write operation. The auxiliary driver transistor may be added to a 5-transistor single-sided-write SRAM cell or to a 7-transistor single-sided-write SRAM cell. The SRAM cell may ... | 04/17/2012 |
| 8154912 | Volatile memory elements with soft error upset immunity Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected... | 04/10/2012 |
| 8134862 | Semiconductor memory device and semiconductor device An object is to provide a semiconductor memory device which holds data of an SRAM or a flip-flop circuit and holds data in the SRAM while electric power is not supplied from a reader or electric power is not enough, without changing a battery for driving a power sup... | 03/13/2012 |
| 8134863 | Semiconductor memory device A semiconductor device according to the present invention includes a first memory cell array in which a plurality of first memory cells are arranged as a matrix, data being read from or written to the first memory cells, and a second memory cell array in which a plu... | 03/13/2012 |
| 8125820 | Semiconductor memory device A memory to which a bit line potential step-down technique is applied is provided. The memory includes an IO block including first transistors which control potentials of first bit lines provided with respect to columns of memory cells, and first logic gates which c... | 02/28/2012 |
| 8116121 | Semiconductor device and manufacturing methods with using non-planar type of transistors Static random access memory cells and methods of making static random access memory cells are provided. The static random access memory cells contain two non-planar pass-gate transistors, two non-planar pull-up transistors, two non-planar pull-down transistors. A po... | 02/14/2012 |
| 8040717 | SRAM cell and SRAM device A static random access memory (SRAM) cell includes a first to a fourth semiconductor thin plate that are provided on a substrate and are arranged parallel to each other. On respective semiconductor thin plates, there is formed a first four-terminal double-gate field... | 10/18/2011 |
| 8036023 | Single-event upset immune static random access memory cell circuit A circuit and method are provided in which a six-transistor (6-T) SRAM memory cell is hardened to single-event upsets by adding isolation-field effect transistors (“iso-fets”) connected between the reference voltage Vdd and the field-effect transistors (“fets... | 10/11/2011 |
| 8000131 | Non-volatile field programmable gate array A non-volatile memory device includes a first metal-oxide-semiconductor (CMOS) device coupled to a bit line and a word line and a second CMOS device coupled to the first CMOS device. The second CMOS device is also coupled to a complementary bit line and a complement... | 08/16/2011 |
| 7990759 | Hardened memory cell The memory cell comprises first and second inverter circuits, connected in a loop. First and second decoupling transistors, normally turned off outside the write phases, are respectively connected between an output of the second inverter circuit and first and second... | 08/02/2011 |
| 7990760 | Semiconductor SRAM with alternatively arranged P-well and N-well regions A semiconductor memory device comprises a cell array having a plurality of SRAM cells arranged in a bit line direction and a word line direction orthogonal to said bit line direction in a matrix; and a peripheral circuit arranged adjacent to the cell array in the bi... | 08/02/2011 |
| 7986547 | Semiconductor memory device A semiconductor memory device includes a memory cell array having a plurality of read word lines, a plurality of first and second read bit lines, and a plurality of memory cells arranged in array. The memory cell includes a first and a second cell node in complement... | 07/26/2011 |
| 7978503 | Static semiconductor memory with a dummy call and a write assist operation A dummy memory cell for detection of write completion timing is provided as a replica of a memory cell. When assisting a write operation by power supply control and substrate potential control of the memory cell, the timing of ending the write assist operation is de... | 07/12/2011 |
| 7978504 | Floating gate device with graphite floating gate One or more embodiments relate to a memory device, comprising: a substrate; a charge storage layer disposed over the substrate; and a control gate disposed over the charge storage layer, wherein the charge storage layer or the control gate layer comprises a carbon a... | 07/12/2011 |
| 7965541 | Non-volatile single-event upset tolerant latch circuit A non-volatile single-event upset (SEU) tolerant latch is disclosed. The non-volatile SEU tolerant latch includes a first and second inverters connected to each other in a cross-coupled manner. The gates of transistors within the first inverter are connected to the ... | 06/21/2011 |
| 7965540 | Structure and method for improving storage latch susceptibility to single event upsets A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical co... | 06/21/2011 |
| 7952913 | Back gated SRAM cell One method for operating an SRAM cell includes applying a potential to a back gate of a pair of cross coupled p-type pull up transistors in the SRAM during a write operation. The method includes applying a ground to the back gate of the pair of cross coupled p-type ... | 05/31/2011 |
| 7944735 | Method of making a nanotube-based shadow random access memory Random access memory including nanotube switching elements. A memory cell includes first and second nanotube switching elements and an electronic memory. Each nanotube switching element includes conductive terminals, a nanotube article and control circuitry capable ... | 05/17/2011 |
| 7929333 | Semiconductor memory device A semiconductor memory device includes a sub array including a plurality of memory cells each holding data arranged therein; a memory cell array including a plurality of the sub arrays arranged therein; paired bit lines including a first bit line and a second bit li... | 04/19/2011 |
