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| Number | Title | Issue Date |
| 8189367 | Single event upset hardened static random access memory cell A single event upset (SEU) hardened memory cell to be utilized in static random access memories is disclosed. The SEU hardened memory cell includes a first transistor, a second transistor and a first resistor connected between a source of the first transistor and a ... | 05/29/2012 |
| 8189368 | Cell structure for dual port SRAM A multi-port SRAM cell includes cross-coupled inverters each including a pull-up transistor and at least a pair of pull down transistors. The SRAM cell includes first and second access ports coupled to first and second word line conductors, each access port includin... | 05/29/2012 |
| 8184474 | Asymmetric SRAM cell with split transistors on the strong side An integrated circuit containing an SRAM cell array in which each SRAM cell includes an auxiliary NMOS driver or PMOS load transistor plus a bit-side passgate transistor and a bit-bar-side passgate transistor. An integrated circuit containing an SRAM cell array in w... | 05/22/2012 |
| 8179715 | 8T SRAM cell with four load transistors An integrated circuit containing SRAM cells with auxiliary load transistors on each data node. The integrated circuit also contains circuitry so that auxiliary load transistors in addressed SRAM cells may be biased independently of half-addressed cells. A process of... | 05/15/2012 |
| 8174867 | Negative-voltage generator with power tracking for improved SRAM write ability An integrated circuit structure includes a static random access memory (SRAM) cell; a first power supply node connected to the SRAM cell, wherein the first power supply node is configured to provide a first positive power supply voltage to the SRAM cell; and a bit-l... | 05/08/2012 |
| 8174868 | Embedded SRAM structure and chip An embedded SRAM chip in a 32 nm or smaller technology generation includes a first SRAM array of first SRAM unit cells. Each first SRAM unit cell includes a data latch for data storage and at least two pass gates for data reading and writing access. The cell area is... | 05/08/2012 |
| 8169813 | Method for evaluating SRAM memory cell and computer readable recording medium which records evaluation program of SRAM memory cell A method for evaluating an SRAM memory cell in which the time required for designing the SRAM memory cell can be shortened by evaluating static noise margin in a shortened time. A recording medium which records an evaluation program is also provided. The coordinate ... | 05/01/2012 |
| 8169814 | Schmitt trigger-based finFET SRAM cell The present invention provides a Schmitt trigger-based FinFET static random access memory (SRAM) cell, which is an 8-FinFET structure. A FinFET has the functions of two independent gates. The new SRAM cell uses only 8 FinFET per cell, compared with the 10-FinFET str... | 05/01/2012 |
| 8164944 | Driver circuit and image forming apparatus A driver circuit includes a memory cell for storing data and a data switching circuit. The memory cell includes a first inverter having a first output terminal and a first input terminal and a second inverter having a second output terminal and a second input termin... | 04/24/2012 |
| 8164943 | Soft error robust storage SRAM cells and flip-flops A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary lower storage nodes and complementary upper storage nodes. The upper storage nodes act to limit feedback between the lower storage nodes and are capable of r... | 04/24/2012 |
| 8159862 | Recycling charges A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second ... | 04/17/2012 |
| 8154911 | Memory device and method of writing data to a memory device A memory device includes bitlines, wordlines and a matrix of memory cells arranged in rows and columns. Each of the bitlines is electrically connected to memory cells in one of the columns. Each of the wordlines is electrically connected to memory cells in one of th... | 04/10/2012 |
| 8154910 | Full CMOS SRAM A full complementary metal-oxide semiconductor (CMOS) static random access memory (SRAM) may have a reduced cell size by arranging a word line of a pair of transistors arranged on the uppermost layer of the SRAM. First and second transistors may be arranged on first... | 04/10/2012 |
| 8149612 | Memory array and method of implementing a memory array A memory array having a plurality of memory cells is disclosed, where each memory cell comprises a first inverter having a first transistor coupled between a reference voltage and a first node for receiving input data and a second transistor coupled between the firs... | 04/03/2012 |
| 8144501 | Read/write margin improvement in SRAM design using dual-gate transistors An integrated circuit structure includes a static random access memory (SRAM) cell. The SRAM cell includes a pull-up transistor and a pull-down transistor forming an inverter with the pull-up transistor. The pull-down transistor includes a front gate connected to a ... | 03/27/2012 |
| 8144502 | Static random access memory Included are a memory cell, a first metal interconnection, a variable capacitance circuit and a connection switch. The memory cell includes cross-coupled first and second inverters which are connected to a power supply node. The first metal interconnection is connec... | 03/27/2012 |
| 8139401 | Integrated circuit with a memory matrix with a delay monitoring column An integrated circuit has a matrix of rows and columns of cells (10, 18, 19), each cell (10, 18, 19) comprising a first inverter (100) and a second inverter (102). First columns have a bit-line (12a,b), the first inverter ( | 03/20/2012 |
| 8139400 | Enhanced static random access memory stability using asymmetric access transistors and design structure for same A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations and a plurality of cells lo... | 03/20/2012 |
| 8134861 | Memory access method and semiconductor memory device A semiconductor memory device includes a memory cell array provided with blocks each having a plurality of memory cells arranged in columns and rows, a column selection circuit selecting a column via bit lines based on a column section signal, a word line driver cir... | 03/13/2012 |
| 8125811 | Content-addressable memory A CAM includes first and second memory units. The first memory unit includes: a first data memory cell for storing a first data bit; a first comparison circuit for comparing a first search bit with the first data bit to determine if there is a match, and outputting ... | 02/28/2012 |
| 8120975 | Memory having negative voltage write assist circuit and method therefor A method of writing data to a selected column of a memory includes selecting a first column. The data writing is initiated by applying a logic high to a first bit line of the first column and a first potential to a second bit line of the first column that is lower t... | 02/21/2012 |
| 8116118 | Memory cell provided with dual-gate transistors, with independent asymmetric gates The invention concerns a random access memory cell comprising: at least one first plurality of symmetrical dual-gate transistors (TL1T, TL1F, TD1T, TD1F, TL... | 02/14/2012 |
| 8116120 | Depletion-mode MOSFET circuit and applications Positive logic circuits, systems and methods using MOSFETs operated in a depletion-mode, including electrostatic discharge protection circuits (ESD), non-inverting latches and buffers, and one-to-three transistor static random access memory cells. These novel circui... | 02/14/2012 |
| 8116119 | Desensitizing static random access memory (SRAM) to process variations A static random access memory (SRAM) can include a plurality of columns forming a memory array, wherein each column comprises a plurality of memory cells coupled to bitlines and wordlines, and a write replica circuit generating a signal when data has been written to... | 02/14/2012 |
| 8111542 | 8T low leakage SRAM cell This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters having a storage node, and a NMOS transistor having a gate terminal, a first and a second source/drain terminal connected to the storage node, a read word... | 02/07/2012 |
| 8111543 | Semiconductor memory device An SRAM cell includes one pair of drive transistors, one pair of load transistors, one pair of write access transistors, one pair of read drive transistors, and one pair of access transistors. A voltage source potential is supplied to drains of the read drive transi... | 02/07/2012 |
| 8107279 | Semiconductor integrated circuit and manufacturing method therefor High manufacturing yield is realized and variations in threshold voltage of each MOS transistor in a CMOS.SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation... | 01/31/2012 |
| 8107278 | Semiconductor storage device A semiconductor storage device includes a memory cell array having a plurality of SRAM cells arranged along a pair of bit lines that extend along a first direction. A read circuit is arranged for each column at one side of the memory cell array and detects a potenti... | 01/31/2012 |
| 8085580 | System for bitcell and column testing in SRAM A system comprises a storage cell coupled to multiple bitlines and a transistor that couples to the multiple bitlines in parallel with the storage cell. The transistor is activated while the storage cell is read. ... | 12/27/2011 |
| 8085579 | Semiconductor memory device In a memory cell, a margin for data preservation is provided while suppressing a current consumption associated with a low-power consumption mode. A MOS transistor has the same structure as NMOS transistors included in each of memory cells. When a low-power consumpt... | 12/27/2011 |
| 8081502 | Memory elements with body bias control An integrated circuit with memory elements is provided. The memory elements may have memory element transistors with body terminals. Body bias control circuitry may supply body bias voltages that strengthen or weaken memory element transistors to improve read and wr... | 12/20/2011 |
| 8081503 | Volatile memory elements with minimized area and leakage current Arrays of memory elements may have data lines and address lines. Each memory element may have five transistors. An address decoder may receive an undecoded address signal and may produce a corresponding decoded address signal. The decoded version of the address sign... | 12/20/2011 |
| 8077499 | Semiconductor integrated memory circuit and trimming method thereof A latch circuit includes first and second inverters connected in a cross-coupling manner at a first node and a second node. A voltage application circuit applies a hot carrier generation voltage for generating hot carrier at a transistor included in the first invert... | 12/13/2011 |
| 8077500 | Volatile memory elements with soft error upset immunity Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strength... | 12/13/2011 |
| 8072798 | Semiconductor memory device The semiconductor memory device includes: an inverter pair of a cross-coupled first and second inverters; a first transfer transistor including a front gate and a back gate connected to a first node to which an output terminal of the first inverter and an input term... | 12/06/2011 |
| 8072796 | Memory with five-transistor bit cells and associated control circuit Memory employing a plurality of five-transistor memory bit cells in a memory matrix and a power supply control circuit that is configured to provide a simultaneous full clear to all of the memory bit cells is described herein. ... | 12/06/2011 |
| 8072799 | Semiconductor integrated circuit device The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells ... | 12/06/2011 |
| 8072797 | SRAM cell without dedicated access transistors A Static Random Access Memory (SRAM) cell without dedicated access transistors is described. The SRAM cell comprises a plurality of transistors configured to provide at least a pair of storage nodes for storing complementary logic values represented by corresponding... | 12/06/2011 |
| 8059440 | Content-addressable memory A content-addressable memory (CAM) comprises a first CAM cell and a second CAM cell. The first CAM cell stores a first data bit, and compares the first data bit with a first search bit to determine if they are matched. The second CAM cell stores a second data bit, a... | 11/15/2011 |
| 8059452 | Cell structure for dual port SRAM An integrated circuit and methods for laying out the integrated circuit are provided. The integrated circuit includes a first and a second transistor. The first transistor includes a first active region comprising a first source and a first drain; and a first gate e... | 11/15/2011 |
