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| Number | Title | Issue Date |
| 7933142 | Semiconductor memory cell and array using punch-through to program and read same An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the transistor includes a source region, a drain region, a gate, a gate insulator, and a body region having a stor... | 04/26/2011 |
| 7933143 | Capacitorless DRAM and methods of operating the same A capacitorless DRAM and methods of manufacturing and operating the same are provided. The capacitorless DRAM includes a source, a drain and a channel layer, formed on a substrate. A charge reserving layer is formed on the channel layer. The capacitorless DRAM inclu... | 04/26/2011 |
| 7548447 | Semiconductor memory device and methods thereof A semiconductor memory device and methods thereof. The example semiconductor memory device may include a semiconductor substrate, a first source line and a second source line oriented in a first direction, the first and second source lines not in contact with each o... | 06/16/2009 |
| 7443713 | Integrated semiconductor memory and method for operating a semiconductor memory An integrated semiconductor memory device includes at least one memory cell, at least one sense amplifier and a pair of bit lines connected to each sense amplifier, where each memory cell includes a selection transistor and a storage capacitor. The storage capacitor... | 10/28/2008 |
| 7391640 | 2-transistor floating-body dram A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during tim... | 06/24/2008 |
| 7388796 | Method for testing memory under worse-than-normal conditions A method for testing a memory with cell plates and bit-line plates comprises putting the memory in a test mode, applying a test pattern to the memory, then providing a first voltage higher than Vdd/2 to the cell plate when writing a ‘1’ to a predetermined cell, ... | 06/17/2008 |
| 7388786 | Semiconductor storage apparatus A semiconductor storage apparatus including cell arrays, each having a plurality of memory cells connected to a pair of first and second bit lines; and sense amplifiers, each being provided corresponding to the pair of first and second bit lines and sensing data rea... | 06/17/2008 |
| 7365433 | High-frequency semiconductor device and method of manufacturing the same The object of the present invention is to implement an enhancement in a noise eliminating characteristic of a wiring compatibly with promotion of microfabrication and simplification of a manufacturing process. Upper and side surfaces of a wiring (6) for trans... | 04/29/2008 |
| 7359246 | Memory device with a ramp-like voltage biasing structure based on a current generator A memory device includes a plurality of memory cells each one for storing a value, at least one reference cell, biasing means for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage having a substantially monotone time p... | 04/15/2008 |
| 7342842 | Data storage device and refreshing method for use with such device A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit 16... | 03/11/2008 |
| 7323726 | Method and apparatus for coupling to a common line in an array A method and apparatus for coupling to a common line in an array. Gate structures of an integrated circuit are formed. Source and drain regions adjacent to the gate structures are implanted. A source contact from a metal Vss line to a source region is formed. Dopant... | 01/29/2008 |
| 7304340 | Semiconductor storage elements, semiconductor device manufacturing methods therefor, portable electronic equipment and IC card A semiconductor storage element has a memory function body on opposite sides of a gate electrode formed on a semiconductor substrate. Each end of source/drain regions is located in the semiconductor substrate just under the memory function body and offset with respe... | 12/04/2007 |
| 7301799 | Memory cell array A memory cell array is formed by providing a plurality of memory cells along a substrate, where each of the memory cells includes a storage element and an access transistor. A plurality of bit lines are formed that extend along a first direction of the substrate. A ... | 11/27/2007 |
| 7295043 | Differential output circuit for improving bandwidth A differential output circuit includes first and second inputs, first and second outputs, a resistor element connected between the outputs, first and second N-channel MISFETs, and first and second P-channel MISFETs. The inputs respectively receive first and second c... | 11/13/2007 |
| 7292479 | Memory device with multistage sense amplifier A memory device with a multistage sense amplifier is disclosed. According to one aspect, a memory device has a memory cell array having at least one memory cell, at least one sense amplifier. Binary data signals read out from the memory cell are amplified and evalua... | 11/06/2007 |
| 7266032 | Memory device having low Vpp current consumption A method of performing a self refresh of memory cells in a memory device. The memory device includes a first group of cell blocks and a second group of cell blocks and each cell block of the first group shares at least one sense amplifier with a cell block of the se... | 09/04/2007 |
| 7257015 | Semiconductor memory device having a floating storage bulk region The disclosure concerns a semiconductor memory device including a plurality of transistors. Each of the transistors has a first data state having a first threshold voltage and a second data state having a second threshold voltage. A sense amplifier is provided for a... | 08/14/2007 |
| 7242060 | Semiconductor memory device including an SOI substrate A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located bet... | 07/10/2007 |
| 7242608 | Semiconductor memory device having a floating storage bulk region capable of holding/emitting excessive majority carriers A semiconductor memory device includes: a semiconductor layer which is formed on an insulating layer; a plurality of transistors which are formed on the semiconductor layer and arranged in a matrix form, each of the transistors having a gate electrode, a source regi... | 07/10/2007 |
| 7241658 | Vertical gain cell A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating body between a drain region and a source region, and a second vertical MOS transistor merged with the se... | 07/10/2007 |
| 7224024 | Single transistor vertical memory gain cell A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region therebetween. A gate opposes the floating body region and is separated... | 05/29/2007 |
| 7221060 | Composite alignment mark scheme for multi-layers in lithography Systems and/or methods are disclosed for aligning multiple layers of a multi-layer semiconductor device fabrication process and/or system utilizing a composite alignment mark. A component is provided to form the composite alignment mark, such that a first portion of... | 05/22/2007 |
| 7221582 | Method and system for controlling write current in magnetic memory Methods and apparatuses are disclosed for controlling the write current in magnetic memory. In some embodiments, the method includes: providing a current in a plurality of memory write lines (where the write lines may be magnetically coupled to at least one memory e... | 05/22/2007 |
| 7211867 | Thin film memory, array, and operation method and manufacture method therefor A memory cell which is formed on a fully depleted SOI or other semiconductor thin film and which operates at low voltage without needing a conventional large capacitor is provided as well as a memory cell array. The semiconductor thin film is sandwiched between firs... | 05/01/2007 |
| 7208799 | Floating body cell dynamic random access memory with optimized body geometry A semiconductor device includes a semiconductor substrate; a first insulation layer formed on the semiconductor substrate; a semiconductor layer insulated from the semiconductor substrate by the insulation layer; a source region of a first conduction type and a drai... | 04/24/2007 |
| 7177197 | Latched programming of memory and method Operating voltages to a group of memory cells in an array are supplied via access lines such as word lines and bit lines. The capacitance of associated nodes of the memory cells can latch some of these voltages. Memory operation can continue using the latched voltag... | 02/13/2007 |
| 7170807 | Data storage device and refreshing method for use with such device A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit 16... | 01/30/2007 |
| 7149109 | Single transistor vertical memory gain cell A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region therebetween. A gate opposes the floating body region and is separated... | 12/12/2006 |
| 7141835 | Semiconductor memory device having memory cells requiring no refresh operation A memory cell includes first and second data holding portions for holding stored data and its inverted data. First and second p channel TFT compensate for charges leaked from first and second capacitors, respectively. A first (second) access transistor has first and... | 11/28/2006 |
| 7139184 | Memory cell array A memory cell array includes memory cells, bit lines running along a first direction, word lines running along a second direction perpendicular to the first direction, and continuous active area lines, wherein transistors are at least partially formed in the active ... | 11/21/2006 |
| 7135697 | Spin readout and initialization in semiconductor quantum dots A semiconductor quantum dot device converts spin information to charge information utilizing an elongated quantum dot having an asymmetric confining potential along its length so that charge movement occurs during orbital excitation. A single electron sensitive elec... | 11/14/2006 |
| 7136295 | Semiconductor arrangement A semiconductor arrangement on a semiconductor chip includes a number of lines of a first type that extend outwardly from an inner region toward an outer region of the semiconductor chip. A number of lines of a second type are arranged around the inner region of the... | 11/14/2006 |
| 7133303 | Dynamic type semiconductor memory apparatus A dynamic type semiconductor memory apparatus performs an operation of continuous column access at a high speed while minimizing an increase of a chip size. The dynamic type semiconductor memory apparatus includes first and second memory cell groups divided based on... | 11/07/2006 |
| 7120072 | Two transistor gain cell, method, and system A two transistor memory cell includes a write transistor and a read transistor. When reading the memory cell, the read transistor is turned on, and a voltage develops on a read bit line. ... | 10/10/2006 |
| 7110291 | Nano tube cell, and semiconductor device having nano tube cell and double bit line sensing structure The present invention discloses a nano tube cell, and a semiconductor device having the nano tube cell and a double bit line sensing structure. The cell array circuit includes a plurality of top sub cell arrays, a plurality of bottom sub cell arrays, a main bit line... | 09/19/2006 |
| 7095118 | High-Frequency semiconductor device with noise elimination characteristic The object of the present invention is to implement an enhancement in a noise eliminating characteristic of a wiring compatibly with promotion of microfabrication and simplification of a manufacturing process. Upper and side surfaces of a wiring (6) for trans... | 08/22/2006 |
| 7072205 | Floating-body DRAM with two-phase write A row of floating-body single transistor memory cells is written to in two phases. ... | 07/04/2006 |
| 7042783 | Magnetic memory One embodiment of a magnetic memory includes a memory cell configured to provide a first state, and a sensing circuit. The sensing circuit is configured to charge a capacitor through the memory cell in the first state and discharge the capacitor through the memory c... | 05/09/2006 |
| 7038937 | Dynamic memory word line driver scheme A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The circuit eliminates the need for a double-boot-strapping circuit... | 05/02/2006 |
| 7030405 | Method and apparatus for resistance variable material cells The present invention is related to methods and apparatus to produce a memory cell or resistance variable material with improved data retention characteristics and higher switching speeds. In a memory cell according to an embodiment of the present invention, silver ... | 04/18/2006 |
