Microwave Oven With Removable Storage Cassette in Dashboard of Motor Vehicle
A microwave oven adapted for use within a motor vehicle dashboard area. The microwave oven has a removable storage cassette, and slidable platforms for securing and serving containers of beverages and foods.
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| Number | Title | Issue Date |
| 4080590 | Capacitor storage memory A semiconductor memory produced in a unipolar technology includes a cell which has an inversion capacitor with one terminal connected to a bit/sense line, the other terminal is coupled to a source of charges by a pulse from a word line. To provide a word ... | 03/21/1978 |
| 4079358 | Buried junction MOS memory capacitor target for electron beam addressable memory and method of using same A buried junction MOS memory capacitor target device for electron beam addressable READ/WRITE memories is described along with a method of using the same. The memory capacitor target structure comprises a planar semiconductor substrate of various degrees ... | 03/14/1978 |
| 4074239 | Memory cell with nondestructive recall In a semiconductor memory cell in which binary data is represented by the density of minority carriers stored in the inversion regions of two isolated MIS capacitors, a method of nondestructively recalling the datum stored therein is described. In this me... | 02/14/1978 |
| 4070652 | Acousto-electric signal convolver, correlator and memory An acousto-electric device provides a memory for a reference signal and provides for the convolution or correlation of input signals with the reference signal. The reference signal is transduced onto a piezoelectric surface to establish an electric field ... | 01/24/1978 |
| 4069475 | MOS Dynamic random access memory having an improved sense and restore circuit In a memory circuit, first and second bit line portions, each having a plurality of memory cells coupled thereto as provided for reading and writing electrical potentials into and out of the coupled memory cells. A bistable flip-flop type sensing amplifie... | 01/17/1978 |
| 4069474 | MOS Dynamic random access memory having an improved sensing circuit In a memory circuit, first and second bit line portions, each having a plurality of memory cells coupled thereto are provided for reading and writing electrical potentials into and out of the coupled memory cells. A bistable flip-flop type sensing amplifi... | 01/17/1978 |
| 4069447 | Stabilized high-efficiency sampling system An improved electronic sampling circuit combines the merits of a high-efficiency sampling system with the DC stability of the more standard feedback sampling system. The stabilized high-efficiency sampling system is very useful for sampling high-speed eve... | 01/17/1978 |
| 4064491 | Information memory for storing information in the form of electric charge carriers and method of operating thereof An information memory for storing information in the form of electric charge carriers has at least one dynamic storage element which is arranged upon a surface of at least one substrate made of semiconductor material and doped with a given basic type dopi... | 12/20/1977 |
| 4062037 | Semiconductor memory device A semiconductor memory device, which comprises: a P-type semiconductor material comprising on the surface thereof, an N-type doped layer, one surface region of the substrate adjoining the doped layer being used as a gate region, and further comprising in ... | 12/06/1977 |
| 4055837 | Dynamic single-transistor memory element for relatively permanent memories The invention relates to a dynamic single-transistor memory element whereby the information may be stored for long periods of time without an energy supply. The invention also provides for a dynamic single-transistor memory element having the capability o... | 10/25/1977 |
| 4045783 | MOS one transistor cell RAM having divided and balanced bit lines, coupled by regenerative flip-flop sense amplifiers, and balanced access circuitry A dynamic MOS one transistor cell memory having a plurality of divided bit lines and a corresponding plurality of flip-flop sense amplifiers. Each bit line being divided into two electrically balanced parts which run adjacent and parallel to each other, a... | 08/30/1977 |
| 4044340 | Semiconductor memory A random access type semiconductor memory comprises a pair of data line halves arranged in parallel, a plurality of word lines orthogonal to the data line halves, a multiplicity of memory cells, each of which is arranged at either one of the cross points ... | 08/23/1977 |
| 4040016 | Twin nodes capacitance memory A semiconductor memory produced in a unipolar technology includes a cell which has a pair of inversion capacitors with one terminal of each capacitor connected to one of a pair of bit/sense lines, the other terminal of each capacitor is coupled to a sourc... | 08/02/1977 |
| 4040017 | Injected charge capacitor memory A semiconductor memory produced in a unipolar technology includes a cell which has an inversion capacitor with one terminal connected to a bit/sense line, the other terminal is coupled to a source of charges by a pulse from a word line. The charges are pr... | 08/02/1977 |
| 4039860 | Amplifier arrangement for detecting logic signals from a capacitance source Write-in and/or read out amplifier for a capacitive source of logic signals, wherein the input of an inverting amplifier stage including insulated-gate field effect transistors is, in a first phase, connected to the output by a first switching unit and su... | 08/02/1977 |
| 4038646 | Dynamic MOS RAM An improved dynamic MOS RAM employing capacitive storage memory cells having a single active device per cell. The RAM includes several improved circuits and techniques which reduce power consumption and pattern sensitivity and which also provide a higher ... | 07/26/1977 |
| 4031522 | Ultra high sensitivity sense amplifier for memories employing single transistor cells This disclosure relates to a high impedance regenerative differential sense amplifier for use with an integrated circuit memory array of single transistor cells. Each of the sense amplifiers is formed of a cross coupled latch connected to the respective c... | 06/21/1977 |
| 4027294 | Compensation element for dynamic semiconductor stores, and method of operating the same A compensation element and method for operating the same, for use with dynamic semiconductor stores, employing a main storage element operatively connected to a word line and a bit line, and an evaluator circuit operatively connected to the bit line, by m... | 05/31/1977 |
| 4023147 | Associative capacitive storage circuits For associative operation of a storage circuit, two field-effect transistors form one storage cell, i. e. that together with associated capacitors they store either a 1 or a 0. A word line is connected to one electrode of each field-effect transistor in a... | 05/10/1977 |
| 4021788 | Capacitor memory cell A dynamic capacitive memory cell having a storage node formed at the common junction of a fixed access capacitor and two MOS voltage variable capacitors. Data represented in the form of stored charge is written into the storage node through the fixed acce... | 05/03/1977 |
| 4017883 | Single-electrode charge-coupled random access memory cell with impurity implanted gate region A charge-coupled random access memory cell is formed in a semiconductor body divided into three adjacent regions. The first region has an impurity diffused therein and serves alternately as a source and a drain for charge carriers. The second or gate regi... | 04/12/1977 |
| 4014036 | Single-electrode charge-coupled random access memory cell A charge-coupled random access memory cell is formed in a semiconductor body divided into three adjacent regions. The first region has an impurity diffused therein and serves alternately as a source and a drain for charge carriers. The second or gate regi... | 03/22/1977 |
| 4012757 | Contactless random-access memory cell and cell pair A one device per bit random access memory cell and array is constructed with integrated circuit MOSFET transistors as the memory cell switching elements. Information transfer is accomplished by transferring incremental charges between a capacitor to a sen... | 03/15/1977 |
| 4004284 | Binary voltage-differential sensing circuits, and sense/refresh amplifier circuits for random-access memories In one example, a generally conventional flip-flop circuit is used, including a pair of input field-effect transistors having their gates connected respectively to a pair of circuit nodes A and B. During a preset portion of the cycle, both nodes A and B a... | 01/18/1977 |
| 4003035 | Complementary field effect transistor sense amplifier for one transistor per bit ram cell A random access memory includes a plurality of one-transistor storage cells. A plurality of sense-write conductors are included, each connected to a plurality of storage cells in a row of storage cells. A plurality of regenerative sense amplifiers are eac... | 01/11/1977 |
| 4003034 | Sense amplifier circuit for a random access memory An improved sense amplifier circuit for a Random Access Memory (RAM) having 1-transistor memory cells which is completely dynamic in that it does not dissipate D.C. power during operation and is suitable for location at one end of a memory cell array. The... | 01/11/1977 |
| 4003036 | Single IGFET memory cell with buried storage element A semiconductor read/write memory comprised of an array of cells, each having a single active element that is a IGFET device formed in a recess with one source or drain region located directly above and its other source or drain region located within a bu... | 01/11/1977 |
| 3995260 | MNOS charge transfer device memory with offset storage locations and ratchet structure A MNOS charge transfer device memory having permanent storage locations displaced laterally from the charge transfer channel is disclosed. The device structure controls charge spreading to prevent charge-to-be-transferred from reaching the portion of the ... | 11/30/1976 |
| 3986180 | Depletion mode field effect transistor memory system The present invention relates to an integrated memory system comprising an array of depletion mode field effect transistors operated in a common control electrode mode to provide an array with the density of metal oxide semiconductor field effect transist... | 10/12/1976 |
| 3983543 | Random access memory read/write buffer circuits incorporating complementary field effect transistors Disclosed is a Read/Write Buffer circuit for a random access memory integrated circuit chip based upon complementary enhancement mode field effect transistor technology.... | 09/28/1976 |
| 3983545 | Random access memory employing single ended sense latch for one device cell A monolithic random access memory having a plurality of groups of storage cells, each storage cell of each group being adapted to store an electrical manifestation of a binary 1, or an electrical manifestation of a binary 0, a sense latch for each of said... | 09/28/1976 |
| 3983544 | Split memory array sharing same sensing and bit decode circuitry A split random access memory array is integrated with a read only storage array and shares the same sense and bit decode circuitry. Each bit line of the integrated array is provided with an isolation switch between the random access and read only portions... | 09/28/1976 |
| 3979734 | Multiple element charge storage memory cell An integrated circuit memory system includes capacitive storage memory cells capable of storing n bits of information on n capacitors associated with multiple emitters of a bilaterally conductive bipolar transistor. Each capacitor is coupled to a separate... | 09/07/1976 |
| 3976984 | Level shifting circuit device A level shifting circuit device comprises a first terminal connected to a high voltage power source, a P channel type IG-FET whose source and substrate electrodes are connected to said first terminal, means for applying a first pulse signal to the gate el... | 08/24/1976 |
| 3968480 | Memory cell A memory system has a data storage element connected by a first memory read device to a first memory output line and by a second memory read device to a second memory output line. A first and a second decoder are connected to the first and second memory r... | 07/06/1976 |
| 3959782 | MOS circuit recovery time An MOS device is usually connected to a power supply through an MOS device which is connected so that load current can be supplied to the MOS circuit when it is turned on and leakage current can be supplied thereto when it is turned off. It has been found... | 05/25/1976 |
| 3955181 | Self-refreshing random access memory cell A memory cell comprising field effect transistors for use in a random access memory array. The cell is of the dynamic type wherein data is stored on capacitive elements, and is self-refreshing; no circuitry external to the array is needed for refresh, oth... | 05/04/1976 |
| 3953836 | Acoustic storage device for high-frequency electrical signals The present invention relates to a storage device for high-frequency electrical signals. In the units employed for the storage of electrical signals and consisting of a capacitor in series with a diode constituted by an insulated electrode 10 applied to a... | 04/27/1976 |
| 3949381 | Differential charge transfer sense amplifier A differential charge transfer amplifier which functions as a sensing and regenerating circuit responsive to binary information represented by the level of charge in a stored charge memory cell is disclosed. The sense amplifier includes a pair of dummy ce... | 04/06/1976 |
| 3943496 | Memory clocking system A solid state memory employs a plurality of memory cells each capable of storing either of two different binary values. The memory cells require periodic application of a refresh pulse to the memory cell to, without rewriting, enhance at least one of the ... | 03/09/1976 |