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| Number | Title | Issue Date |
| 7327626 | Self refresh control device Disclosed herein is a self refresh control device for reducing a current leakage of transistors in off-state. The apparatus for controlling a voltage used in a semiconductor memory device includes a first voltage supplying block for supplying a first voltage to the ... | 02/05/2008 |
| 7327622 | Semiconductor device A semiconductor device includes: a first sense amplifier; a first bit line coupled to the first sense amplifier; a second bit line disposed next to the first bit line and electrically coupled to a constant-voltage source; and a first reference cell, including: a fir... | 02/05/2008 |
| 7327596 | Electrostatic capacitance detection device and smart card An electrostatic capacitance detection device, for detecting electrostatic capacitance that changes in accordance with a distance from a target object to read surface contours of the target object, can sense electrostatic capacitance highly accurately even with usin... | 02/05/2008 |
| 7324379 | Memory device and method of operating the same with high rejection of the noise on the high-voltage supply line A memory device has an array of memory cells. A column decoder is configured to address the memory cells. A charge-pump supply circuit generates a boosted supply voltage for the column decoder. A connecting stage is arranged between the supply circuit and the column... | 01/29/2008 |
| 7324394 | Single data line sensing scheme for TCCT-based memory cells A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge ... | 01/29/2008 |
| 7323361 | Packaging system for semiconductor devices A package system for integrated circuit (IC) chips and a method for making such a package system. The method uses a solder-ball flip-chip method for connecting the IC chips onto a lead frame that has pre-formed gull-wing leads only on the source/gate side of the chi... | 01/29/2008 |
| 7324367 | Memory cell and method for forming the same A semiconductor memory cell structure having 4 F2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the su... | 01/29/2008 |
| 7323928 | High capacitance integrated circuits An integrated circuit providing high equivalent capacitance ranging from a few tens of picofarads to a few nanofarads is presented. The integrated circuit includes active integrated circuit components, requires no external capacitor, and is substantially insensitive... | 01/29/2008 |
| 7324396 | Sense amplifier organization for twin cell memory devices A semiconductor memory device is provided that uses a single wordline to access both storage cells of a so-called twin cell. A memory device comprises a plurality of wordlines and a plurality of bitlines in an array, with a plurality of storage cells at certain inte... | 01/29/2008 |
| 7321143 | Ion-sensitive field effect transistor and method for producing an ion-sensitive field effect transistor An ion-sensitive field effect transistor includes a substrate on which there are formed a source region and a drain region. Above a channel region, the ion-sensitive field effect transistor has a gate with a sensitive layer including a metal oxide nitride mixture an... | 01/22/2008 |
| 7321110 | Solid state image pickup device and camera An solid state image pickup device including a plurality of photoelectric conversion regions (PD1, PD2) for generating carriers by photoelectric conversions to accumulate the generated carriers, an amplifying unit for amplifying the carriers, being com... | 01/22/2008 |
| 7321502 | Non volatile data storage through dielectric breakdown A method is described that induced dielectric breakdown within a capacitor's dielectric material while driving a current through the capacitor. The current is specific to data that is being written into the capacitor. The method also involves reading the data by int... | 01/22/2008 |
| 7321514 | DRAM memory cell arrangement The present invention relates to a memory cell arrangement comprising a multiplicity of DRAM memory cells which are arranged in cell rows and cell columns and the selection transistor of which comprises in each case a first gate electrode and also a rear side electr... | 01/22/2008 |
| 7319607 | Ferroelectric memory A ferroelectric memory, upon reading of a memory cell array, in which the plate line PL is charged to the power supply potential VDD by a driving control circuit prior to driving of the relevant word line WL. The bit lines BL and /BL are charged to the potential VDD... | 01/15/2008 |
| 7319616 | Negatively biasing deselected memory cells In one embodiment, the present invention includes a method to supply a negative voltage to at least one deselected wordline of a memory array. Further, while the negative voltage is supplied to deselected wordlines, a positive voltage may be supplied to a selected w... | 01/15/2008 |
| 7319608 | Non-volatile content addressable memory using phase-change-material memory elements A non-volatile content addressable memory cell comprises: a first phase change material element, the first phase change material element having one end connected to a match-line; a first transistor, the first transistor having a gate connected to a word-line, a sour... | 01/15/2008 |
| 7319629 | Method of operating a dynamic random access memory cell A method of operating a dynamic random access memory cell is disclosed. The true logic state of a stored bit is rewritten to a first storage node of the memory cell and the complementary logic state of the stored bit is rewritten to a second storage node of the memo... | 01/15/2008 |
| 7319627 | Memory device A sense amplifier circuit for a non-volatile semiconductor memory device is used to output data written in a selected non-volatile memory cell and is constructed as a current mirror circuit including a first mirror transistor and a second mirror transistor of a mirr... | 01/15/2008 |
| 7319611 | Bitline transistor architecture for flash memory A memory array includes a buried diffusion region, a first source line that supplies electrical power to the buried diffusion region, a second source line that supplies electrical power to the buried diffusion region, a first bitline transistor having a first channe... | 01/15/2008 |
| 7319613 | NROM flash memory cell with integrated DRAM A memory device that is comprised of a dynamic random access memory (DRAM) capacitor and a nitride read only memory (NROM) transistor. The memory device provides multiple modes of operation including a DRAM mode using the capacitor and a non-volatile random access m... | 01/15/2008 |
| 7317657 | Semiconductor memory device, system with semiconductor memory device, and method for operating a semiconductor memory device The invention relates to a semiconductor memory device, a system with a semiconductor memory device, and a method for operating a semiconductor memory device, comprising the steps of reading out a data value, in particular a CAS latency time data value (CL) stored i... | 01/08/2008 |
| 7317641 | Volatile memory cell two-pass writing method A method is set forth for writing volatile memory cells embodied on an integrated circuit and taking the form of an array of volatile memory cells including a plurality of word lines and a plurality of bit lines. In use, a first write operation is performed on at le... | 01/08/2008 |
| 7316959 | Semiconductor device and method for fabricating the same The semiconductor device comprises a semiconductor layer 18 formed on an insulation layer 16, a gate electrode 22 formed on the semiconductor layer with a gate insulation film 20 formed therebetween, a source/drain region 24 formed... | 01/08/2008 |
| 7315478 | Internal voltage generator for a semiconductor memory device Provided is an internal voltage generator for a semiconductor memory includes: a first internal voltage drive device for driving an internal voltage in response to a first reference voltage corresponding to a target level of an internal voltage; and a second interna... | 01/01/2008 |
| 7313011 | Ferroelectric memory devices having a plate line control circuit Ferroelectric memory devices include a ferroelectric memory cell. The ferroelectric memory cell has at least one bit line and a plate line. A control circuit drives the at least one bit line with write data substantially concurrently with activation of the plate lin... | 12/25/2007 |
| 7313041 | Sense amplifier circuit and method A semiconductor device memory device (300) can include a sense amplifier (302) enabled according to a first sense signal (setn) and a second sense signal (setp). In a sense operation, a first sense signal (setn) can be driven to a first, below ground p... | 12/25/2007 |
| 7313026 | Semiconductor device Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried o... | 12/25/2007 |
| 7313010 | Circuit for generating a centered reference voltage for a 1T/1C ferroelectric memory A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the referenc... | 12/25/2007 |
| 7313036 | Memory device having open bit line architecture for improving repairability and method of repairing the same In a memory device having an open bit line architecture for improving repairability and a method of repairing the memory device, redundant memory cells used to repair defective cells are included even in first and second edge sub-arrays that are arranged at the edge... | 12/25/2007 |
| 7310257 | Local digit line architecture and method for memory devices having multi-bit or low capacitance memory cells A DRAM array includes for each column a pair of complimentary digit lines that are coupled to a sense amplifier. Each of the global digit lines is selectively coupled to a plurality of local digit lines by respective coupling circuits. The length of the local digit ... | 12/18/2007 |
| 7310273 | Method for controlling precharge timing of memory device and apparatus thereof A method for controlling a precharge timing of a memory device is disclosed. The method includes making timing of generation of a signal for determining a precharge timing in a normal operation and a signal for determining a precharge timing in a refresh operation d... | 12/18/2007 |
| 7310279 | Semiconductor memory device and semiconductor integrated circuit In a semiconductor memory device, third and fourth transistors are configured as a vertical structure. The third transistor is laminated over a first transistor, and the fourth transistor is laminated over a second transistor, whereby a reduction in cell area is ach... | 12/18/2007 |
| 7310258 | Memory chip architecture with high speed operation A semiconductor memory device includes at least one data transmission block including data I/O pads arranged in a major-axis side of the semiconductor memory device; a command and address transmission block including address and command input pads arranged in at lea... | 12/18/2007 |
| 7310356 | Automatic discovery of network core type Systems and methods for automatically discovering the configuration of network and/or communication facilities are provided. The determination generally involves receiving and/or sending at least one test message or packet with special characteristics that normally ... | 12/18/2007 |
| 7310264 | Rectifying charge storage memory circuit A composite rectifying charge storage device, consisting of a rectifier and capacitor which share common elements, is provided in a memory circuit or memory cell. In one form, the memory cell is adapted for alternative operation as a random access memory (RAM) or as... | 12/18/2007 |
| 7310256 | Semiconductor memory device A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing informa... | 12/18/2007 |
| 7307869 | Method and circuit for reading a dynamic memory circuit A method for reading data from a dynamic memory circuit is provided, wherein at least one memory cell can be addressed via a word line and a bit line, wherein the memory cell is connected to a first reading amplifier via the bit line, and wherein a switching element... | 12/11/2007 |
| 7307860 | Static content addressable memory cell A static content addressable memory (CAM) cell. The CAM cell includes a latch having complementary data nodes capacitively coupled to ground, first and second access transistors, each coupled between a data node of the latch and a respective data line. The gates of ... | 12/11/2007 |
| 7301815 | Semiconductor memory device comprising controllable threshould voltage dummy memory cells The present invention provides a semiconductor memory device capable of preventing a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitch of word lines at an end of a memory block. Plural dummy word lines ... | 11/27/2007 |
| 7301830 | Semiconductor memory device and semiconductor device and semiconductor memory device control method A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the c... | 11/27/2007 |
