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| Number | Title | Issue Date |
| 7184337 | Method for testing an integrated semiconductor memory A method for testing an integrated semiconductor memory provides for disturbing memory cells arranged along a first word line by a disturbance signal on an adjacent word line. The memory cells along the first word line and bit lines, respectively, connected to them ... | 02/27/2007 |
| 7184298 | Low power programming technique for a floating body memory transistor, memory cell, and memory array There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or progr... | 02/27/2007 |
| 7180802 | Method of stress-testing an isolation gate in a dynamic random access memory The present invention includes a DRAM array. The DRAM array includes a first memory cell, a second memory cell and an isolation gate formed between the first and second memory cells. The isolation gate is configured to provide electrical isolation between the first ... | 02/20/2007 |
| 7180782 | Read source line compensation in a non-volatile memory Non-volatile memory circuits according to the present invention provide a reference memory having multiple reference cells that are shared among a group of sense amplifiers through an interconnect conductor line. The higher number of reference cells for each referen... | 02/20/2007 |
| 7177220 | Refresh counter with dynamic tracking of process, voltage and temperature variation for semiconductor memory A method and system for DRAM refresh wherein the refresh rate is proportional to the current leakage of one or more sampling cells. The sampling cells selected are representative of the nominal leakage condition of the DRAM array and track the DRAM cell leakage rate... | 02/13/2007 |
| 7177218 | DRAM device with a refresh period that varies responsive to a temperature signal having a hysteresis characteristic A semiconductor device includes a DRAM and a temperature sense circuit. The DRAM has a refresh period that varies responsive to a temperature signal. The temperature sense circuit is configured to generate the temperature signal having a first binary value in respon... | 02/13/2007 |
| 7177213 | Capacitor supported precharging of memory digit lines Circuits and methods are provided for precharging pairs of memory digit lines. The final precharge voltage of the digit lines is different from the average of the digit line voltages prior to precharging. The final precharge voltage can be set by appropriately selec... | 02/13/2007 |
| 7177175 | Low power programming technique for a floating body memory transistor, memory cell, and memory array There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or progr... | 02/13/2007 |
| 7177135 | On-chip bypass capacitor and method of manufacturing the same An on-chip bypass capacitor and method of manufacturing the same, the on-chip bypass capacitor including at least two capacitor arrays, each capacitor array including a first layer connecting the at least two capacitor arrays in series, each capacitor array includin... | 02/13/2007 |
| 7177174 | Ferroelectric memory device having a reference voltage generating circuit A ferroelectric memory device includes a plurality of memory cells, each memory cell includes a ferroelectric capacitor and a transistor, a plate line drive unit capable of providing a first voltage to the memory cell array in response to a plate line drive signal, ... | 02/13/2007 |
| 7176093 | Semiconductor processing methods of forming integrated circuitry Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo impla... | 02/13/2007 |
| 7176745 | Semiconductor device The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS circuit can thus operate stably with lower power consumption, because ... | 02/13/2007 |
| 7176864 | Display memory, driver circuit, display, and cellular information apparatus A display memory able to reduce power consumption, able to generate graphics at a high speed, and not needing memory mapping, a driver circuit, a display using the driver circuit, and a portable information apparatus, wherein a CPU read circuit is connected to one b... | 02/13/2007 |
| 7177215 | Semiconductor memory device operating at high speed and low power consumption A semiconductor integrated circuit device equipped with a memory circuit, which realizes the speeding up of its operation and low power consumption in a simple configuration is provided. At input/output nodes of a sense amplifier including a CMOS latch circuit for p... | 02/13/2007 |
| 7177216 | Twin-cell bit line sensing configuration Twin-cell bit line sensing structures and techniques are provided. Utilizing a folded bit line like structure, with bit line and complementary bit lines located together, sense amplifiers can be between cell arrays. Bit line switches, responsive to activated word li... | 02/13/2007 |
| 7177203 | Data readout circuit and semiconductor device having the same A data readout circuit for reading memory data from a resistance change memory disposed at a point where a bit line and a word line intersect by setting a potential of the bit line to a predetermined bias potential and detecting a current value flowing in the resist... | 02/13/2007 |
| 7173851 | 3.5 transistor non-volatile memory cell using gate breakdown phenomena A programmable memory cell formed useful in a memory array having column bitlines and row wordlines. The memory cell including a breakdown transistor having its gate connected to a program wordline and a write transistor connected in series at a sense node to said b... | 02/06/2007 |
| 7173855 | Current limiting antifuse programming path Method and apparatus are disclosed for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the region responds in a non-linear manner to changes in voltage. In this way a variable resistor or a vari... | 02/06/2007 |
| 7173873 | Device and method for breaking leakage current path A device and a method for breaking the leakage current path, wherein the leakage current is caused by a defect in a memory cell of a memory array, are provided. The device includes a column selection line, a row selection line, a switch device coupled to the column ... | 02/06/2007 |
| 7173844 | Device and method for generating reference voltage in Ferroelectric Random Access Memory (FRAM) A reference voltage generating device that provides a constant reference voltage even with temperature change in a ferroelectric random access memory and a method for driving the same are provided. A device for generating a reference voltage in a ferroelectric rando... | 02/06/2007 |
| 7170807 | Data storage device and refreshing method for use with such device A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit 16... | 01/30/2007 |
| 7170808 | Power saving refresh scheme for DRAMs with segmented word line architecture Techniques and apparatus that may be utilized to reduce current consumption during refresh cycles of DRAM devices that utilize wordline segments are provided. Rather than activate and subsequently de-activate (pre-charge) a master wordline each time a corresponding ... | 01/30/2007 |
| 7170141 | Method for monolithically integrating silicon carbide microelectromechanical devices with electronic circuitry A method of forming electronics and microelectromechanical on a silicon carbide substrate having a slow etch rate is performed by forming circuitry on the substrate. A protective layer is formed over the circuitry having a slower etch rate than the etch rate of the ... | 01/30/2007 |
| 7169666 | Method of forming a device having a gate with a selected electron affinity A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the... | 01/30/2007 |
| 7170792 | Semiconductor device A semiconductor device to output voltages at three levels to a word driver while alleviating the breakdown voltage in the MOS transistor. This invention is comprised of a breakdown-voltage reducing MOS transistor inserted in the word driver and two NMOS transistors ... | 01/30/2007 |
| 7166509 | Write once read only memory with large work function floating gates Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate tra... | 01/23/2007 |
| 7164595 | Device and method for using dynamic cell plate sensing in a DRAM memory cell A memory cell, device, system and method for operating a memory cell are disclosed that utilize an isolated dynamic cell plate. The memory cell includes a first and second pass transistor and a first and second capacitor. The first pass transistor and first capacito... | 01/16/2007 |
| 7164612 | Test circuit for measuring sense amplifier and memory mismatches Post-manufacture compensation for a sensing offset can be provided, at least in part, by selectively exposing one of a pair of cross-coupled transistors in a sense amplifier to a bias voltage selected to cause a compensating shift in a characteristic of the exposed ... | 01/16/2007 |
| 7164520 | Packaging for an interferometric modulator A package is made of a transparent substrate having an interferometric modulator and a back plate. A non-hermetic seal joins the back plate to the substrate to form a package, and a desiccant resides inside the package. A method of packaging an interferometric modul... | 01/16/2007 |
| 7164188 | Buried conductor patterns formed by surface transformation of empty spaces in solid state materials A plurality of buried conductors and/or buried plate patterns formed within a monocrystalline substrate is disclosed. A plurality of empty-spaced buried patterns are formed by drilling holes in the monocrystalline substrate and annealing the monocrystalline substrat... | 01/16/2007 |
| 7164593 | Semiconductor integrated circuit A storage section, at least one writing section, and at least one reading section are provided on a substrate. A storage-section substrate region in which the storage section is formed, at least one writing-section substrate region in which each writing section is f... | 01/16/2007 |
| 7161792 | Capacitor cell, semiconductor device and process for manufacturing the same A capacitor cell for reducing noise in a high drive cell includes a plurality of vias for supplying power to an interconnection layer positioned over the capacitor cell from an upper interconnection layer, so that the resistance of the power supply path is reduced. | 01/09/2007 |
| 7161204 | DRAM capacitor structure with increased electrode support for preventing process damage and exposed electrode surface for increasing capacitor area A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature siz... | 01/09/2007 |
| 7161372 | Input system for an operations circuit An integrated device includes a redundant bond pad for accessing internal circuitry in the event that the main bond pad for that circuitry is difficult to access with testing equipment. Signals from the redundant bond pad are biased to ground during normal operation... | 01/09/2007 |
| 7158410 | Integrated DRAM-NVRAM multi-level memory An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a... | 01/02/2007 |
| 7158435 | Fuse circuit and semiconductor integrated circuit device A fuse circuit has an actual fuse circuit block and a fuse monitor circuit. The actual fuse circuit block stores fuse information; on the other hand, the fuse monitor circuit monitors whether a supply voltage has reached an information capturable voltage at which th... | 01/02/2007 |
| 7158399 | Digital data apparatuses and digital data operational methods Digital data apparatuses and digital data operational methods are described. According to one embodiment, a digital data apparatus includes a semiconductive substrate comprising a node location configured to receive an electrical charge of a single bit of digital in... | 01/02/2007 |
| 7158400 | Method of operating dynamic random access memory A method of operating a dynamic random access memory (DRAM) using a bit line and a bit line bar is disclosed. The DRAM stores data by using a charge storage device, which is coupled to the bit line via a switch device. A voltage drop occurs when the switch device is... | 01/02/2007 |
| 7158401 | Methods for machine detection of at least one aspect of an object, methods for machine identification of a person, and methods of forming electronic systems Electronic systems including Si/Ge substrates. The electronic systems can include data storage devices and/or logic devices having active regions extending into a crystalline Si/Ge material. An entirety of the portion of an active region within the crystalline Si/Ge... | 01/02/2007 |
| 7157768 | Non-volatile flash semiconductor memory and fabrication method In a semiconductor memory, a plurality of FinFET arrangements with trapping layers or floating gate electrodes as storage mediums are present on respective top sides of fins made from semiconductor material. The material of the gate electrodes is also present on two... | 01/02/2007 |
