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| Number | Title | Issue Date |
| 8111564 | Setting controller termination in a memory controller and memory device interface in a communication bus A DRAM and memory controller are coupled during driver training to reduce mismatches. The impedances of the system are controlled through a termination at the controller to yield improvements in timing margins. The coupling of the components on a shared electrical b... | 02/07/2012 |
| 8089801 | Semiconductor memory device and method of forming the same The present invention discloses a semiconductor memory device comprising a source, a drain, a floating gate, a control gate, a recess channel and a gated p-n diode. The said p-n diode connects said floating gate and said drain. The said floating gate is for charge s... | 01/03/2012 |
| 8059451 | Multiple valued dynamic random access memory cell and thereof array using single electron transistor Provided is a multi-valued dynamic random access memory (DRAM) cell using a single electron transistor (SET). The multi-valued DRAM cell using the SET applies different refresh signals to a load current transistor for controlling current supply to the SET and a volt... | 11/15/2011 |
| 8054676 | Memory system such as a dual-inline memory module (DIMM) and computer system using the memory system A memory system (250) includes a plurality of memory devices (260) adapted to be coupled to an interface (140), an indicator (272) for indicating a type of the plurality of memory devices (260), and an override circuit (280)... | 11/08/2011 |
| 8050080 | Random access memory with CMOS-compatible nonvolatile storage element in series with storage capacitor Random access memory with CMOS-compatible nonvolatile storage element in series with storage capacitor is described herein. Embodiments may include memory devices and systems that have plurality of row lines, column lines, and memory cells each of which comprising a... | 11/01/2011 |
| 8045365 | Apparatus and method for self-refreshing dynamic random access memory cells A dynamic random access memory (DRAM) having DRAM cells coupled to wordlines and bitlines. In a self-refresh mode, the cells coupled with the even numbered rows retain main data previously stored therein and the assistant data, which is logically opposite to the mai... | 10/25/2011 |
| 8036020 | Circuit for reading a charge retention element for a time measurement A method and a circuit for reading an electronic charge retention element for a temporal measurement, of the type including at least one capacitive element whose dielectric exhibits a leakage and a transistor with insulated control terminal for reading the residual ... | 10/11/2011 |
| 8036021 | Semiconductor memory device A memory cell array includes a plurality of memory cells arranged at intersections of bit line pairs and word lines. Each memory cell includes a first transistor having one main electrode connected to a first bit line, a second transistor having one main electrode c... | 10/11/2011 |
| 8031512 | Multiple-valued DRAM Provided herein is an MV DRAM device for storing multiple value levels using an SET device. The device includes one or more word lines; one or more bitlines; a DRAM cell connected to intersections of the word lines and the bitlines; a current source transistor havin... | 10/04/2011 |
| 8031513 | Semiconductor device and method of operating thereof A semiconductor device includes: a memory cell; a precharge circuit; a negative potential applying circuit; and a sense amplifier. The memory cell is connected to a first bit line and store data. The precharge circuit is connected to the first and second bit lines a... | 10/04/2011 |
| 8023314 | Dynamic memory word line driver scheme A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The circuit eliminates the need for a double-boot-strapping circuit... | 09/20/2011 |
| 8009460 | Device and method for using dynamic cell plate sensing in a DRAM memory cell A memory cell, device, system and method for operating a memory cell utilize an isolated dynamic cell plate. The memory cell includes a first and second pass transistor and a first and second capacitor. The first pass transistor and first capacitor and the second pa... | 08/30/2011 |
| 8009459 | Circuit for high speed dynamic memory A memory cell includes a write access transistor coupled between a storage node and a write bit line, and active during a write cycle responsive to a voltage on a write word line; a read access transistor coupled between a read word line and a read bit line, and act... | 08/30/2011 |
| 7990755 | DRAM including pseudo negative word line For increasing retention time in DRAM, pseudo negative word line scheme is realized such that voltage of a local bit line pair is always higher than that of an unselected word line for applying negative gate voltage, but selected word line is asserted to a pre-deter... | 08/02/2011 |
| 7983070 | DRAM tunneling access transistor In one embodiment, a first transistor is comprised of a first p+ source region doped in an n-well in the substrate and a first n+ drain region doped on one side at the top of the pillar. A second transistor is comprised of a second p+ source region doped into the se... | 07/19/2011 |
| 7978502 | Method of programming a memory device of the one-time programmable type and integrated circuit incorporating such a memory A memory device of the irreversibly electrically programmable type is provided with a memory cell having a dielectric zone disposed between a first electrode and second electrode. An access transistor is connected in series with the second electrode, and an auxiliar... | 07/12/2011 |
| 7969765 | Sense amplifier for semiconductor memory device A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line d... | 06/28/2011 |
| 7961498 | Leakage compensation circuit for Dynamic Random Access Memory (DRAM) cells A Dynamic Random Access Memory (DRAM) cell comprising a leakage compensation circuit. The leakage compensation circuit allows a compensation current from a source to flow to the memory cell storage node of the DRAM cell to compensate the leakage current from the mem... | 06/14/2011 |
| 7952944 | System for providing on-die termination of a control signal bus A system for providing on-die termination (ODT) of a control signal bus. The system includes a memory device that includes a plurality of data bus connectors, one or both of a load signal connector and a reset signal connector, a control bus connector, an ODT, and a... | 05/31/2011 |
| 7944732 | Integrated capacitor with alternating layered segments A capacitor in an integrated circuit (“IC”) has a first node plate link formed in a first metal layer of the IC electrically connected to and forming a portion of a first node of the capacitor extending along a first axis (y) and a second node plate link formed ... | 05/17/2011 |
| 7940549 | DRAM positive wordline voltage compensation device for array device threshold voltage and voltage compensating method thereof The configurations of a DRAM positive wordline voltage compensation device and a voltage compensating method thereof are provided in the present invention. The proposed device includes a comparator having a first input terminal receiving a positive wordline voltage ... | 05/10/2011 |
| 7933140 | Techniques for reducing a voltage swing Techniques for reducing a voltage swing are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for reducing a voltage swing comprising: a plurality of dynamic random access memory cells arranged in arrays of rows and co... | 04/26/2011 |
| 7933141 | Semiconductor memory device In a semiconductor memory device, a memory cell is connected with a local sense amplifier and a global sense amplifier via a local bit line and a global bit line. The local sense amplifier is a single-ended sense amplifier including a single MOS transistor, which de... | 04/26/2011 |
| 7911825 | Multi-port memory based on DRAM core A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports. ... | 03/22/2011 |
| 7903449 | Semiconductor memory device A semiconductor memory device (e.g. DRAM) is constituted of a memory cell array including a plurality of memory cells, a plurality of word line drivers, a plurality of sense amplifiers, and a plurality of dummy capacitors. The memory cells, each of which includes a ... | 03/08/2011 |
| 7903480 | Integrated circuit, and method for transferring data An integrated circuit and a method for transferring data is provided. One embodiment provides a method for transferring data in an integrated circuit. The method includes driving a first line in accordance with data to be transferred. The data is transmitted from th... | 03/08/2011 |
| 7894240 | Method and apparatus for reducing charge trapping in high-k dielectric material In one embodiment, an integrated circuit includes a memory array having a plurality of capacitors for storing data of an initial state in the memory array in an initial state. The integrated circuit also includes circuitry for occasionally inverting the data stored ... | 02/22/2011 |
| 7894241 | Memory cell array and semiconductor memory device including the same A memory cell array with open bit line structure includes a first sub memory cell array, a second sub memory cell array, a sense-amplifier/precharge circuit, first capacitors and second capacitors. The first sub memory cell array is activated in response to a first ... | 02/22/2011 |
| 7872902 | Integrated circuit with bit lines positioned in different planes An integrated circuit includes a memory cell array including a plurality of memory cells. A first plurality of bit lines is positioned in a first plane. The first plurality of bit lines is electrically coupled to a first set of the memory cells. A second plurality o... | 01/18/2011 |
| 7864559 | Dram memory device with improved refresh characteristic A semiconductor memory device and a method for operating the same can improve a refresh characteristic of the semiconductor memory device by physically writing only logic low data in memory cells, irrespective of logic level of input data, either high or low. The se... | 01/04/2011 |
| 7859890 | Memory device with multiple capacitor types An integrated circuit includes a memory array portion and a support circuitry portion arranged on a semiconductor substrate. An insulative layer is formed on the semiconductor substrate. Data storage capacitors are located in the memory array portion and extending t... | 12/28/2010 |
| 7859889 | Semiconductor memory device In a two-transistor gain cell structure, a semiconductor memory device capable of stable reading without malfunction and having small-area memory cells is provided. In a two-transistor gain cell memory having a write transistor and a read transistor, a write word li... | 12/28/2010 |
| 7852690 | Multi-chip package for a flash memory An electronic system includes a flash memory die having multiple flash memory cells. Each flash memory cell is operable to store at least four bits of data. A second die includes a controller for accessing the flash memory cells. DRAM is used by the controller to te... | 12/14/2010 |
| 7848134 | FB DRAM memory with state memory A memory chip with a plurality of FB DRAM cells, having a word line coupled to a first FB DRAM cell and a second FB DRAM cell is disclosed. The memory chip further has a first bit line coupled to the first FB DRAM cell, and a first state memory circuit coupled to th... | 12/07/2010 |
| 7821812 | Low-power DRAM and method for driving the same A dynamic random access memory includes: an address latch configured to latch a row address in response to a row address strobe (RAS) signal and latch a column address in response to a column address strobe (CAS) signal; a row decoder configured to decode the row ad... | 10/26/2010 |
| 7768814 | Method and apparatus for measuring statistics of dram parameters with minimum perturbation to cell layout and environment The present invention provides a method for measuring statistics of dynamic random access memory (DRAM) process parameters for improving yield and performance of a DRAM. The basic principles for measuring capacitance are similar to charge based capacitance (CBCM), h... | 08/03/2010 |
| 7768813 | DRAM with word line compensation In one embodiment, a DRAM is provided that includes: a word line intersecting with a pair of bit lines, the DRAM including a memory cell at each intersection, each memory cell including an access transistor adapted to couple a storage cell to the corresponding bit l... | 08/03/2010 |
| 7755924 | SRAM employing a read-enabling capacitance Embodiments of the present disclosure provide a memory element, a method of constructing a memory element, a method of operating a memory cell, an SRAM cell and an integrated circuit. In one embodiment, the memory element includes a pair of cross-connected CMOS inve... | 07/13/2010 |
| 7751228 | Dielectric relaxation memory A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for t... | 07/06/2010 |
| 7742324 | Systems and devices including local data lines and methods of using, making, and operating the same Disclosed are methods, systems and devices, including a device having a fin field-effect transistor with a first terminal, a second terminal, and two gates. In some embodiments, the device includes a local data line connected to the first terminal, at least a portio... | 06/22/2010 |
