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Vladimir Zworykin, television pioneer ; Talking about an invention in which he played a critical role.
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| Number | Title | Issue Date |
| 7254680 | Semiconductor integrated circuit and data processing system To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, dat... | 08/07/2007 |
| 7253052 | Method for forming a storage cell capacitor compatible with high dielectric constant materials Described are integrated circuit electrodes and method for fabricating an electrode, which include, in an embodiment forming a silicon, first portion of the electrode in a lower region of a substrate opening. The method may further include forming a second portion o... | 08/07/2007 |
| 7254051 | Semiconductor memory device and various systems mounting them A semiconductor memory device comprises a plurality of memory cells each having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to the source terminal, wherein the plurality of memory cells are connected in seri... | 08/07/2007 |
| 7251184 | Semiconductor memory device A semiconductor memory device is provided which has a hierarchical bit line structure and can perform a high-speed read operation even with a low voltage. A subarray 12 includes a first MOS transistor PD1 for charging a main bit line MBL1 and a ... | 07/31/2007 |
| 7251150 | Radiation-hardened programmable device A method of programming a radiation-hardened integrated circuit includes the steps of supplying a prototype device including an SRAM memory circuit or programmable key circuit to a customer, having the customer develop working data patterns in the field in the same ... | 07/31/2007 |
| 7251153 | Memory A memory capable of suppressing disturbance causing disappearance of data from a nonselected memory cell is provided. This memory applies a second voltage of polarity reverse to that of a first voltage applied to a nonselected memory cell in a read operation to at l... | 07/31/2007 |
| 7248502 | Non-volatile semiconductor memory device When a voltage level detector detects that a supply voltage reaches a recovery voltage level that requires a recovery operation, a signal generator generates a recovery operation instructing signal for instructing the recovery operation. The recovery operation instr... | 07/24/2007 |
| 7248493 | Memory system having improved random write performance A memory system includes a ferroelectric memory, flash EEPROM, control circuit, and interface circuit. The control circuit is configured to control the ferroelectric memory and flash EEPROM. The interface circuit is configured to communicate externally. Data is prog... | 07/24/2007 |
| 7247524 | Manufacturing method of wiring substrate After a first adhesive layer having high adhesion to a supporting base is locally formed, a second adhesive layer having low adhesion to the supporting base is formed all over the supporting base so as to cover the first adhesive layer. When a wiring structure is se... | 07/24/2007 |
| 7248514 | Semiconductor memory device A semiconductor memory device enabling efficient repair of defects by using limited redundant memory while suppressing a drop of access speed accompanied with the repair of defects of the memory, wherein a first memory array is divided into a plurality of memory reg... | 07/24/2007 |
| 7248080 | Power supply switching at circuit block level to reduce integrated circuit input leakage currents Leakage currents at IC inputs can be avoided while the IC is disabled by providing a switch that is responsive to deactivation of an enable input to isolate functional circuitry of the IC from one of the power supply nodes of the IC. This eliminates power supply cur... | 07/24/2007 |
| 7248510 | Circuits that generate an internal supply voltage and semiconductor memory devices that include those circuits An internal supply voltage generation circuit is provided that is within a semiconductor memory device, and that is configured to generate an internal supply voltage to a memory array in the semiconductor memory device. The internal supply voltage generation circuit... | 07/24/2007 |
| 7248495 | Semiconductor memory device Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data ... | 07/24/2007 |
| 7248499 | Layout for NAND flash memory array having reduced word line impedance A memory array including a first region in which a first memory sub-array is located and a second region separated from the first region in which a second memory sub-array is located. The first and second memory sub-arrays have flash memory cells coupled to a plural... | 07/24/2007 |
| 7248524 | Operating temperature optimization in a ferroelectric or electret memory In a heating and temperature control system for a data storage apparatus comprising at least one matrix-addressable ferroelectric or electret memory device, Joule heating means are provided in the memory device, a temperature determining means is connected with cont... | 07/24/2007 |
| 7248145 | Radio frequency identification transponder A radio frequency identification transponder including a power supply and a dynamic memory array which stores data. When power from the power supply ceases the data in the dynamic memory array is validly maintained for a predetermined period of time. The dynamic mem... | 07/24/2007 |
| 7245527 | Nonvolatile memory system using magneto-resistive random access memory (MRAM) A non-volatile memory system (230) includes a magnetoresistive random access memory (MRAM) (232) including a plurality of magnetoresistive memory cells, a floating-gate nonvolatile memory (234) including a plurality of floating-gate memory cells... | 07/17/2007 |
| 7245523 | Bistable magnetic device using soft magnetic intermediary material Roughly described, a magnetic structure includes an electrically conductive path for carrying current flow, a soft magnetic material with high permeability value in magnetic communication with the current flow so that it can be magnetized in either of two directions... | 07/17/2007 |
| 7245518 | Ferroelectric memory A ferroelectric memory includes a memory cell array having a plurality of memory cells with ferroelectric capacitors arranged therein, a plurality of word lines, a plurality of plate lines, and a plurality of plate line selection circuits. An L-th plate line selecti... | 07/17/2007 |
| 7245517 | Ferroelectric random access memory Four memory cells each obtained by connecting a ferroelectric capacitor in parallel to a transistor are connected in series with each other to constitute a cell block. A sense amplifier circuit is arranged on a one-end side in a column direction every four cell bloc... | 07/17/2007 |
| 7242604 | Switchable element A memory element, logic element or sensor element is provided, which element comprises a switchable first magnetic component exhibiting a ferromagnetic or ferrimagnetic behaviour and comprising at least two magnetic domains with different magnetization directions an... | 07/10/2007 |
| 7242619 | Reading circuit and method for a nonvolatile memory device Described herein is a reading circuit for a nonvolatile memory device, wherein the currents flowing through an array memory cell to be read, and a reference memory cell with known contents, are converted into an array voltage and, respectively, into a reference volt... | 07/10/2007 |
| 7242606 | Storage apparatus and semiconductor apparatus A storage apparatus includes memory devices each having a storage element with a characteristic that the application of an electric signal not lower than a first threshold signal allows the storage element to shift from a high resistance value state to a low resista... | 07/10/2007 |
| 7240275 | Logical data block, magnetic random access memory, memory module, computer system and method A logical data block in a MRAM is disclosed. The logical data block comprises magnetic memory cells formed at intersections of hard-axis generating conductors and an easy-axis generating conductor. The logical data block may further be configured in size by a presel... | 07/03/2007 |
| 7239554 | Nonvolatile memory device and method of improving programming characteristic A method of programming a non-volatile memory device includes activating a first pump to generate a bitline voltage, and after the bulk voltage reaches a target voltage, detecting whether the bitline voltage is less than a detection voltage. When the bitline voltage... | 07/03/2007 |
| 7238978 | Ferroelectric memory device A ferroelectric memory device has a high performance, includes no Pb, and can be directly mounted onto an Si substrate. The ferroelectric memory device includes a (001)-oriented BiFeO3 ferroelectric layer 5 with a tetragonal structure, which is for... | 07/03/2007 |
| 7236415 | Sample and hold memory sense amplifier A memory sense amplifier includes a sample and hold circuit followed by a differential amplifier. The sample and hold circuit samples a reference voltage on a bit line of a memory circuit when the sense amplifier is reset and a signal voltage on the same bit line wh... | 06/26/2007 |
| 7236414 | Local sense amplifier in memory device A memory device includes a decoder that sets an operational control signal and a column select line signal at a first logical level simultaneously. In addition, a local sense amplifier has at least one switching device that is turned on by the operational control si... | 06/26/2007 |
| 7235490 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device comprises preparing a working film to be processed, forming an adhesion improving region on the working film for increasing an adhesion between the working film and a mask material containing carbon, forming the mask ... | 06/26/2007 |
| 7235830 | Semiconductor device and process for manufacturing the same The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at on... | 06/26/2007 |
| 7236387 | Writing to ferroelectric memory devices A ground potential is applied to a first word line coupled to a control gate of a selected ferroelectric memory cell in an array of ferroelectric memory cells. A fraction of a programming voltage is applied to other word lines coupled to control gates of non-selecte... | 06/26/2007 |
| 7233880 | Adaptive cache algorithm for temperature sensitive memory A temperature sensitive memory, such as a ferroelectric polymer memory, may be utilized as a disk cache memory in one embodiment. If the temperature begins to threaten shutdown, the memory may be transitioned from a write-back to a write-through cache memory. In suc... | 06/19/2007 |
| 7233531 | SRAM cell with horizontal merged devices A merged structure SRAM cell is provided that includes a first transistor and a second transistor. The second transistor gate forms a load resistor for the first transistor and the first transistor gate forms a load resistor for the second transistor. Also provided ... | 06/19/2007 |
| 7230495 | Phase-locked loop circuits with reduced lock time PLL circuits are provided in which a voltage-controlled oscillator (VCO) comprising one or more voltage-controlled delay units (VCDs) is initialized with the control voltage of a voltage-controlled delay line (VCDL) having substantially identical VCDs. In general, V... | 06/12/2007 |
| 7230844 | Thermomagnetically assisted spin-momentum-transfer switching memory A ferromagnetic thin-film based digital memory having a substrate supporting bit structures that are electrically interconnected with information storage and retrieval circuitry and having first and second oppositely oriented relatively fixed magnetization layers an... | 06/12/2007 |
| 7231472 | Input/output byte control device using nonvolatile ferroelectric register An input/output byte control device using a nonvolatile ferroelectric register can maintain compatibility with various memories by selectively controlling bytes of input/output data. Since bytes of input/output data are selectively activated, the compatibility can b... | 06/12/2007 |
| 7227770 | Ferroelectric-type nonvolatile semiconductor memory A ferroelectric-type nonvolatile semiconductor memory comprising a plurality of bit lines and a plurality of memory cells, each memory cell comprising a first electrode, a ferroelectric layer formed at least on said first electrode... | 06/05/2007 |
| 7228393 | Memory interleaving A central processor unit (CPU) accesses memory to read and write data and to read and execute program instructions. A problem arises when accessing slower Flash or electrically programmable read only memory (EPROM) with a faster CPU. A method and system has been dev... | 06/05/2007 |
| 7227769 | Semiconductor memory A bit line is connected to a charge storing circuit through a charge transferring circuit. A control circuit controls charge transferability of the charge transferring circuit according to a change in the voltage of the bit line resulting from a charge read out from... | 06/05/2007 |
| 7224637 | Tri-mode clock generator to control memory array access A clock generator is provided that is compatible with both DDR1 and DDR2 applications. The internal YCLK signal is turned on only when an active read or write occurs on the integrated circuit memory, even though the main chip clock is always running. A... | 05/29/2007 |
