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| Number | Title | Issue Date |
| 7468900 | Semiconductor memory device having a bitline amplified to a positive voltage and a negative voltage In order to omit a reset transistor between a storage node and a cell plate line of a memory cell, a cell plate line is fixed to a potential substantially equal to a ground potential and a bit line is driven with positive and negative voltages. ... | 12/23/2008 |
| 7466579 | Field effect device with a channel with a switchable conductivity A field effect device includes a source electrode, a drain electrode spaced laterally apart from the source electrode, a channel formed between the source electrode and the drain electrode, and a gate electrode separated from the channel by an insulating layer. The ... | 12/16/2008 |
| 7463504 | Active float for the dummy bit lines in FeRAM Methods are described for operating a FeRAM and other such memory devices in a manner that avoids over-voltage breakdown of the gate oxide in memory cells along dummy bit lines used at the edges of memory arrays, the methods comprising floating the dummy bit line du... | 12/09/2008 |
| 7463505 | Semiconductor memory device and electronic apparatus A semiconductor memory device having: a memory cell array with m memory cells arranged in a first direction and n memory cells arranged in a second direction in a grid, each memory cell having a capacitor part using a ferroelectric film, and also having a first term... | 12/09/2008 |
| 7460390 | Ferroelectric memory device When reading first memory cell data in a ferroelectric memory device, voltage on first bit lines changes. Therefore, controllers turn on first transistors in first read-out voltage generators based on the first bit line voltage, and control the first transistors' ch... | 12/02/2008 |
| 7453714 | Over-driven access method and device for ferroelectric memory An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL′ to further enlarge the v... | 11/18/2008 |
| 7443708 | Low resistance plate line bus architecture An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on t... | 10/28/2008 |
| 7443709 | Temperature sensing circuit, voltage generation circuit, and semiconductor storage device A first bit line is connected to a memory cell. A second bit line is connected to a dummy cell having a dummy capacitor, and supplied with an electric potential which is complementary to the electric potential of the first bit line. A sense amplifier compares and am... | 10/28/2008 |
| 7440307 | Memory This memory comprises a bit line, a first word line and a second word line arranged to intersect with the bit line while holding the bit line therebetween and a first ferroelectric film and a second ferroelectric film, having capacitances different from each other, ... | 10/21/2008 |
| 7436691 | Semiconductor storage device, operation method of the same and test method of the same A semiconductor storage device includes a bit line; a word line; a plate line; a ferroelectric capacitor having a ferroelectric substance between electrodes, one of the electrodes being connected to the plate line, the ferroelectric capacitor being capable of storin... | 10/14/2008 |
| 7436689 | Non-volatile semiconductor memory When an address storing/comparing circuit stores no address identical to an external input address in read operation, in a main memory read data is written back to a data storing area after data read therefrom, and data indicating a sum of a predetermined value and ... | 10/14/2008 |
| 7433220 | Two variable resistance elements being formed into a laminated layer with a common electrode and method of driving the same A memory element having a configuration in which contents of recorded data can be judged easily and power consumption can be reduced, and a method of driving the same are provided. A memory element 10 of the present invention includes variable resistance elem... | 10/07/2008 |
| 7433221 | Memory system and semiconductor integrated circuit A ferroelectric memory provided in a memory system stores in advance set data for data write time to memory cells. The set data include two types of data that differ between in a power-on state and in a power-off instruction time, When power is turned on, the set da... | 10/07/2008 |
| 7428162 | Memory device including a plurality of capacitors A memory device including: a lower electrode; a ferroelectric layer formed above the lower electrode; a charge compensation layer formed above the ferroelectric layer and including an oxide having a composition differing from a composition of the ferroelectric layer... | 09/23/2008 |
| 7428160 | Nonvolatile programmable logic circuit A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPG... | 09/23/2008 |
| 7426130 | Ferroelectric RAM device and driving method A ferroelectric RAM (Random Access Memory) device includes at least one memory cell constructed of one access transistor operating by a word line enable signal, and one ferroelectric capacitor connected between a bit line and the access transistor. The device has a ... | 09/16/2008 |
| 7423925 | Memory A memory capable of performing a refresh operation uncompetitively with an internal access operation also when an external access operation is non-cyclically performed is obtained. This memory comprises an external access detection portion detecting an external acce... | 09/09/2008 |
| 7424559 | Input/output upper and lower byte control device using nonvolatile ferroelectric register An input/output byte control device using a nonvolatile ferroelectric register can maintain compatibility with various memories by selectively controlling bytes of input/output data. Since bytes of input/output data are selectively activated, the compatibility can b... | 09/09/2008 |
| 7420802 | Disk array device A disk array device including a logic mounting unit which mounts a cache memory which temporarily stores data transferred from a high-level device and performs control to write the data stored in the cache memory to a plurality of memory devices at the time of power... | 09/02/2008 |
| 7420833 | Memory A memory capable of suppressing disturbance causing disappearance of data in a nonselected memory cell is provided. This memory comprises a memory cell array including a bit line, a word line arranged to intersect with the bit line and memory cells connected between... | 09/02/2008 |
| 7417886 | Ferroelectric random access memory Four memory cells each obtained by connecting a ferroelectric capacitor in parallel to a transistor are connected in series with each other to constitute a cell block. A sense amplifier circuit is arranged on a one end side in a column direction every four cell bloc... | 08/26/2008 |
| 7417885 | Data carrier system and data saving/restoring method thereof A data carrier system includes: a first memory, which is a ferroelectric memory; a second memory; a polarization canceling circuit for canceling polarization of the first memory in accordance with an instruction given thereto; and a control circuit for making data a... | 08/26/2008 |
| 7417528 | RFID device having nonvolatile ferroelectric memory device A RFID device has a nonvolatile ferroelectric memory including a memory cell array area supplied only with a high voltage and a peripheral area supplied with a low voltage, thereby reducing power consumption. The RFID device includes an antenna adapted and configure... | 08/26/2008 |
| 7414876 | Nonvolatile ferroelectric memory device having power control function A nonvolatile ferroelectric memory device having a power control function improves a sensing margin by stably controlling a power applied to a cell capacitor. The sensing margin of a cell can be improved by controlling an operation voltage of the cell depending on a... | 08/19/2008 |
| 7414881 | Magnetization direction control method and application thereof to MRAM A magnetization direction control method for controlling magnetization directions of first to third ferromagnetic layers (11-13) within a synthetic antiferromagnet structure (10A) having the first to the third ferromagnetic layers (11-... | 08/19/2008 |
| 7411841 | Memory having storage means A memory capable of inhibiting a non-selected cell from disturbance is provided. This memory comprises a bit line, a word line arranged to intersect with the bit line and first storage means connected between the bit line and the word line, for applying voltages of ... | 08/12/2008 |
| 7411809 | Ferroelectric memory to be tested by applying disturbance voltage to a plurality of ferroelectric capacitors at once in direction to weaken polarization, and method of testing the same A unit cell is formed by a ferroelectric capacitor and first MOS transistor, and a block is formed by connecting a plurality of unit cells in series. The gates of the first MOS transistors in the individual unit cells are connected to word lines, which are selective... | 08/12/2008 |
| 7411810 | One-time programmable memory In the present invention, one-time programmable memory includes a diode as an access device and a capacitor as a storage device, the diode includes four terminals, wherein the first terminal is connected to a word line, the second terminal is connected to one plate ... | 08/12/2008 |
| 7408799 | RFID device having nonvolatile ferroelectric memory device A nonvolatile ferroelectric memory in an RFID device includes a plurality of word lines, and a plurality of banks each including a cell array. The cell array of one of the banks includes a region to be initialized, wherein the region includes a plurality of memory u... | 08/05/2008 |
| 7405959 | Ferroelectric memory device A ferroelectric memory device includes memory cells using ferroelectric capacitors provided at intersections of local bit lines associated with a main bit line and word lines. The ferroelectric memory device includes: first and second local bit lines associated with... | 07/29/2008 |
| 7397686 | Memory system combining flash EEPROM and FeRAM A memory system includes a ferroelectric memory formed by arranging a plurality of memory cells having a ferroelectric capacitor and cell transistor, a flash EEPROM formed by arranging a plurality of memory cells having a floating gate and capable of electrically er... | 07/08/2008 |
| 7397685 | Semiconductor memory device having error checking and correcting circuit A semiconductor memory device includes a memory cell including a ferroelectric capacitor and a cell transistor and storing binary data at a first potential level and a second potential level which is higher than the first potential level, a bit line which reads the ... | 07/08/2008 |
| 7397687 | Ferroelectric memory device having ferroelectric capacitor A ferroelectric memory device includes a cell block, a bit line, and a plate line. The cell block includes a ferroelectric capacitor and a transistor switch. The bit line applies a voltage to one electrode of the ferroelectric capacitor. The plate line applies a vol... | 07/08/2008 |
| 7397624 | Transducers for ferroelectric storage medium A ferroelectric transducer for use with a ferroelectric storage medium includes a read electrode. The read electrode emits a current when a polarity orientation of the read electrode is opposite a polarity orientation of a ferroelectric domain on the storage medium.... | 07/08/2008 |
| 7394677 | Ferroelectric random access memory device, display drive IC and electronic equipment A ferroelectric memory device being short in the bit line direction. The ferroelectric memory device is structured including a first word line extending in the first direction; a plurality of element regions arrayed in the first direction on both sides of the first ... | 07/01/2008 |
| 7394678 | Over-driven access method and device for ferroelectric memory An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL′ to further enlarge the v... | 07/01/2008 |
| 7394684 | Spin-injection magnetic random access memory A spin-injection magnetic random access memory of an aspect of the present invention includes a magnetoresistive element, a unit which writes data into the magnetoresistive element by use of spin-polarized electrons generated by a spin-injection current and which ap... | 07/01/2008 |
| 7388769 | Semiconductor memory device A semiconductor memory device includes plural memory cells MC arranged in a matrix, plural bit lines BL and plural plate line voltage supply lines SCP which are arranged in a row direction, plural sense amplifier circuits SA which are arranged in a column direction ... | 06/17/2008 |
| 7385836 | Ferroelectric random access memory A reference bit line which supplies a reference potential to a sense amplifier circuit is connected to the sense amplifier circuit. A reference potential generating circuit is connected to the reference bit line. The reference potential generating circuit includes a... | 06/10/2008 |
| 7382641 | FeRAM for high speed sensing A non-volatile ferroelectric memory device senses a cell data at high speed. Preferably, the non-volatile ferroelectric memory device includes a plurality of cell array blocks, a plurality of sense amplifier units, a plurality of sense amplifier units, a plurality o... | 06/03/2008 |