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"I hate what they've done to my child...I would never let my own children watch it. "
Vladimir Zworykin, television pioneer ; Talking about an invention in which he played a critical role.
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| Number | Title | Issue Date |
| 7205248 | Method of eliminating residual carbon from flowable oxide fill Methods of forming an oxide layer such as high aspect ratio trench isolations, and treating the oxide substrate to remove carbon, structures formed by the method, and devices and systems incorporating the oxide material are provided. ... | 04/17/2007 |
| 7205620 | Highly reliable amorphous high-k gate dielectric ZrON A gate dielectric and method of fabricating a gate dielectric that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate dielectrics formed from metals such as zirconium are thermodynamically... | 04/17/2007 |
| 7206243 | Method of rewriting a logic state of a memory cell A method of operating a dynamic random access memory cell is disclosed. The true logic state of a stored bit is rewritten to a first storage node of the memory cell and the complementary logic state of the stored bit is rewritten to a second storage node of the memo... | 04/17/2007 |
| 7206221 | Upside-down magnetoresistive random access memory An upside-down MRAM comprises a sense transistor and a plurality of sense lines. A first end of the sense transistor is electrically connected to a low voltage. The sense lines are electrically connected in parallel between a high voltage and a second end of the sen... | 04/17/2007 |
| 7203108 | Reliability test method for a ferroelectric memory device A reliability test method for a ferroelectric memory device having a ferroelectric capacitor evaluates, under acceleration conditions (acceleration temperature T2 and test time t2), whether or not life of retention characteristics of the ferroe... | 04/10/2007 |
| 7203086 | Data reading method, data writing method, and semiconductor memory device In a data reading method, a first reading pulse is applied to a memory cell to generate a first signal corresponding to data stored in the memory cell, reference signal generating data corresponding to a high level side is written to the memory cell, a second readin... | 04/10/2007 |
| 7203099 | Semiconductor memory device for low power condition A semiconductor memory device for reading or writing data from or to a memory cell includes at least one cell array having a plurality of memory cells for outputting a stored data to one of a bit line and a bit line bar in response to inputted address and command; a... | 04/10/2007 |
| 7203128 | Ferroelectric memory device and electronic apparatus A ferroelectric memory device characterized in comprising: a voltage source for generating a predetermined voltage; a first bit line and a second bit line; a first ferroelectric capacitor having one end electrically connected to the first bit line; a first resistanc... | 04/10/2007 |
| 7203124 | System and method for negative word line driver circuit A negative word line driver employs devices to maintain the potential difference between the active word line signal and the inactive word line signal while reducing the need for a significant negative voltage supply. One form of the negative word line driver employ... | 04/10/2007 |
| 7203103 | Ferroelectric memory device and electronic apparatus A ferroelectric memory device equipped with: a voltage source for generating a predetermined voltage; a first ferroelectric capacitor having one end electrically connected to a first bit line; a first resistance having a first resistance value, provided between the ... | 04/10/2007 |
| 7200050 | Memory unit and semiconductor device A memory unit that is capable of operating in a desired operation condition with less power consumption, and a semiconductor device using the memory unit. The memory circuit comprises a cell array in which a plurality of memory cells is arranged, a driver circuit, a... | 04/03/2007 |
| 7199427 | DMOS device with a programmable threshold voltage A DMOS device is provided which is equipped with a floating gate having a first and second electrode in close proximity thereto. The floating gate is separated from one of the first and second electrodes by a thin layer of dielectric material whose dimensions and co... | 04/03/2007 |
| 7199495 | Magnetoelectric devices and methods of using same The operational frequency of existing magnetoelectric materials having metallic or ceramic magnetostrictive materials and ceramic piezoelectric materials may be limited to a few kilohertz due to the presence of eddy-current losses in the metallic magnetostrictive ph... | 04/03/2007 |
| 7200026 | Ferroelectric memory device and electronic device A ferroelectric memory is provided including a ferroelectric capacitor having an end electrically coupled to a bit line; a power source generating a predetermined voltage; a resistance formed between the bit line and the power source; and a switch installed in serie... | 04/03/2007 |
| 7200029 | Ferroelectric storage device A ferroelectric storage device includes a ferroelectric capacitor C1, a bit line BL, a first switching element 103 selectively connecting the ferroelectric capacitor C1 and the bit line BL, a first transistor 203 connected to the bit line... | 04/03/2007 |
| 7200033 | MRAM with coil for creating offset field An MRAM memory chip includes a plurality of magnetoresistive memory cells each including a magnetic tunnel junction having first (fixed) and second (free) magnetic regions, where the second magnetic region includes at least two ferromagnetic layers that are antiferr... | 04/03/2007 |
| 7200031 | Proton and heavy ion SEU resistant SRAM A method and system is disclosed for reducing proton and heavy ion SEU sensitivity of a static random access memory (SRAM) cell. A first passive delay element has been inserted in series with an active delay element in a first feedback path of the SRAM cell, and a s... | 04/03/2007 |
| 7200028 | Ferroelectric memory device and its driving method A ferroelectric memory device equipped with a plurality of memory cells and a control section that stores memory data indicated by a data signal when a write control signal changes from a first logical value to a second logical value, the ferroelectric memory device... | 04/03/2007 |
| 7200027 | Ferroelectric memory reference generator systems using staging capacitors Reference generator systems (108, 130) and methods (200) are presented for providing bitline reference voltages for memory access operations in a ferroelectric memory device (102). The reference generator system (108, 130) comprises a pri... | 04/03/2007 |
| 7196924 | Method of multi-level cell FeRAM Disclosed are use methods, integrated circuits, and manufacturing methods for ferroelectric memory. A data value from multiple data values is received, for example by a state machine controlling the ferroelectric memory. The different data values correspond to diffe... | 03/27/2007 |
| 7196943 | Memory device A semiconductor memory device includes a plurality of memory cells arranged according to a plurality of rows and a plurality of columns. The memory devices further includes a plurality of bit lines, each bit line being associated with a respective column of the plur... | 03/27/2007 |
| 7196957 | Magnetic memory structure using heater lines to assist in writing operations The invention includes a stacked magnetic memory structure. The magnetic memory structure includes a stacked magnetic memory structure. The first layer includes a first plurality of magnetic tunnel junctions. A second layer is formed adjacent to the first layer. The... | 03/27/2007 |
| 7193880 | Plateline voltage pulsing to reduce storage node disturbance in ferroelectric memory Methods (50, 70) and ferroelectric devices (102) are presented, in which pulses (113) are selectively applied to platelines (PL) of one or more non-selected ferroelectric memory cells (106) during memory access operations to mitigate cell... | 03/20/2007 |
| 7193890 | Magnetoresistive effect device, magnetic random access memory, and magnetoresistive effect device manufacturing method A magnetoresistive effect device includes a first ferromagnetic layer having a fixed magnetization direction and having magnetic moment ml per unit area. A nonmagnetic layer contacts with the first ferromagnetic layer and has an amplitude hi of roughness of an inter... | 03/20/2007 |
| 7193881 | Cross-point ferroelectric memory that reduces the effects of bit line to word line shorts A memory constructed from a dielectric layer sandwiched between a plurality of word conductors and a plurality of bit line conductors is disclosed. The dielectric layer includes a layer of ferroelectric material, and has first and second surfaces. The word conductor... | 03/20/2007 |
| 7193876 | Content addressable memory (CAM) arrays having memory cells therein with different susceptibilities to soft errors A CAM array has at least one row therein containing a plurality of memory cells with different susceptibilities to soft errors. The memory cells having reduced susceptibilities to soft errors include those used in check bit cells and/or CAM cells containing valid bi... | 03/20/2007 |
| 7192827 | Methods of forming capacitor structures The invention includes a method of forming a capacitor structure. A first electrical node is formed, and a layer of metallic aluminum is formed over the first electrical node. Subsequently, an entirety of the metallic aluminum within the layer is transformed into on... | 03/20/2007 |
| 7193882 | Semiconductor memory device To shorten the time of a test for detecting deteriorated capacitors, a semiconductor memory device having a 2T2C type memory cell structure is designed in such a way that a voltage VBL of a bit line pair which determines a voltage to be applied to ferroelectric memo... | 03/20/2007 |
| 7193893 | Write once read only memory employing floating gates Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate tra... | 03/20/2007 |
| 7193337 | System and method utilizing a solid state power controller (SSPC) for controlling an electrical load of a variable frequency three-phase power source A solid state power controller (SSPC) (100) includes a power switching controller (30) and power switching devices (PSDs) (20A, 20B, 20C) for controlling each phase of a multiple-phase load to switch-on or -off at a zero-crossing p... | 03/20/2007 |
| 7193823 | Magnetoresistive device exhibiting small and stable bias fields independent of device size variation The present invention relates generally to the magnetic information storage technology, and particularly, to magnetic recording disc drives including a sensor having a giant magnetoresistance (GMR) based spin valve structure or a tunneling magnetoresistance(TMR) bas... | 03/20/2007 |
| 7193264 | Floating gate transistors A floating gate MOS transistor comprises one or more control gates, an active channel, and at least one floating gate disposed between the control gate(s) and the active channel. First and second non-linear resistances couple the floating gate to first and second co... | 03/20/2007 |
| 7190606 | Test mode control device using nonvolatile ferroelectric memory A test mode control device using a nonvolatile ferroelectric memory enables a precise test of characteristics of a memory cell array by changing a reference voltage and timing regulated for a memory cell test in a software system without extra processes. In an embod... | 03/13/2007 |
| 7191286 | Data redundancy in individual hard drives A method and system are disclosed for recovering lost data with redundancy in an individual hard drive. A mirroring-type process is used in a single hard drive to maintain a backup copy of all data stored on that hard drive. The hard drive maintains two copies of th... | 03/13/2007 |
| 7190339 | Ferroelectric memory device and display drive IC A ferroelectric memory device capable of structurally reducing data deterioration. In this ferroelectric memory device, bitlines are hierarchized, and sub-bitlines subordinate to the bitlines through sub-bitline select switches are provided in each of a plurality of... | 03/13/2007 |
| 7187579 | Non-volatile ferromagnetic memory having sensor circuitry shared with its state change circuitry A ferromagnetic memory cell is disclosed having a base (21), oriented in a horizontal plane, a bit (19), made of a ferromagnetic material, and a sense/write line (20), positioned proximate the bit (19) sufficient to detect the directed po... | 03/06/2007 |
| 7187602 | Reducing memory failures in integrated circuits Memory reliability is improved by using redundancy to repair errors detected by ECC. In one embodiment, redundancy repairs errors which cannot be corrected by ECC. The redundancy can employ the use of electronic fuses, enabling repairs after an IC containing the mem... | 03/06/2007 |
| 7188282 | Tamper resistant shadow memory An integrated circuit comprising a processor and memory, the memory storing a set of data representing program code and/or an operating value, wherein each bit of the data is stored as a bit/inverse-bit pair in corresponding pairs of physically adjacent bit cells in... | 03/06/2007 |
| 7187195 | Parallel compression test circuit of memory device A parallel compression test circuit of a memory device disperses peak current and reduce noise by operating input/output amplifiers at different timings in a parallel compression test mode. The parallel compression test circuit comprises an input/output amplificatio... | 03/06/2007 |
| 7187587 | Programmable memory address and decode circuits with low tunnel barrier interpoly insulators Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory device includes a number of address lines and a number of output lines wherein the address lines and the ou... | 03/06/2007 |
