Class 365/104 - Transistors

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter wherein the semiconductor storage element
No. of patents: 741
Last issue date: 05/22/2012

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Number	Title	Issue Date
8184466	Semiconductor storage device and ROM generator According to one embodiment, a semiconductor storage device includes a first memory cell, a second memory cell and a third memory cell. The first memory cell forms a connection path used for storage of data. The second memory cell varies a connection place from a co...	05/22/2012
8125815	Transistor bit cell ROM architecture An apparatus and method for providing a read-only memory (ROM) bit cell having one each of a PMOS transistor and an NMOS transistor, which has reduced static and dynamic electric power losses, are described. In particular, the bit cell does not require a pre-charge ...	02/28/2012
8120939	ROM cell having an isolation transistor formed between first and second pass transistors and connected between a differential bitline pair A semiconductor memory cell array includes an elongated continuous active region. First and second pass transistors are formed in the elongated continuous active region and form part of first and second adjacent memory cells, respectively, of a column of memory cell...	02/21/2012
8064239	Memory circuit with quantum well-type carrier storage Data is stored in a quantum-well type structure with double gate control. According to an example embodiment, a transistor-based data storage circuit includes a gate, a back gate and a semiconductor channel between the gate and the back gate. Carriers are stored in ...	11/22/2011
8054668	Method and apparatus for storing data in a write-once non-volatile memory In an illustrative embodiment, a memory cell comprises a first and a second MOSFET, wherein the first MOSFET undergoes a process to modify the threshold voltage such that a modified threshold voltage represents a first stored logic value. By determining which one of...	11/08/2011
8050077	Semiconductor device with transistor-based fuses and related programming method A transistor-based fuse structure is realized in a semiconductor device having a semiconductor substrate, transistor devices formed on the semiconductor substrate, and the transistor-based fuse structure formed on the semiconductor substrate. The transistor-based fu...	11/01/2011
7940546	ROM array A ROM array is provided, comprising a plurality of columns of memory cells, wherein each column of memory cells is coupled to a shared bit line which is shared by that column of memory cells and an adjacent column of memory cells. Each column of memory cells has its...	05/10/2011
7920403	ROM cell array structure A semiconductor memory cell array is disclosed which comprises an elongated continuous active region, a first transistor formed in the elongated continuous active region, the first transistor forming a first single-transistor memory cell, a second transistor also fo...	04/05/2011
7898836	Masked memory cells An array of masked memory cells including a first memory cell in a first column and a second memory cell in a second different column, wherein the first memory cell is capable of being accessed, so as to output, dependent on a first binary mask signal, a first binar...	03/01/2011
7869250	ROM semiconductor integrated circuit device having a plurality of common source lines In a semiconductor integrated circuit device having a volatile memory high-speed operation is enabled and the density of the memory can be enhanced. The volatile memory includes a word line, a complementary bit line having bit lines, a plurality of common source lin...	01/11/2011
7869251	SRAM based one-time-programmable memory Disclosed is a method and device for providing fast-response One-Time-Programmable (OTP) memory based on SRAM memory technology and the inherent breakdown characteristics of a MOS transistor. Each memory cell of an SRAM memory cell circuit is connected to a programm...	01/11/2011
7821806	Nonvolatile semiconductor memory circuit utilizing a MIS transistor as a memory cell A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/dra...	10/26/2010
7760537	Programmable ROM A programmable ROM includes first and second field effect transistors serially connected between first and second power source terminals, a third field effect transistor having a gate connected to a word line and used for data transfer between a first bit line and t...	07/20/2010
7751225	Dense read-only memory In one embodiment, a read-only memory (ROM) is provided that includes: a plurality of word lines; a plurality of bit lines; a plurality of memory cell transistors arranged in rows corresponding to the word lines such that if a word line is asserted the corresponding...	07/06/2010
7719872	Write-once nonvolatile memory with redundancy capability A nonvolatile memory, such as a write-once memory, includes a memory cell array that has first memory cells and at least one second memory cell. The memory also includes a first writing circuit that is capable of writing data to the first memory cells and the second...	05/18/2010
7663904	Operating method of one-time programmable read only memory The present invention provides a method of operating a one-time programmable read only memory (OTPROM). The OTPROM includes at least a select transistor, an electrode and a dielectric layer disposed on a substrate, wherein the electrode is set up on the source regio...	02/16/2010
7660143	Multibit ROM memory The invention concerns a ROM comprising a set of memory points arranged in rows and columns, each memory point capable of storing two bits of data and comprising a single switch controllable to connect together first and second terminals of said switch, each of said...	02/09/2010
7660142	Device with memory and method of operating device A method of operating an electronic device includes storing a first plurality of bits of digital information in a memory using a first number of memory cells in parallel. The first plurality of bits of digital information are for operating the device when operating ...	02/09/2010
7649762	Area efficient high performance memory cell Embodiments for an area efficient high performance memory cell comprising a transistor connected to one of a bit line and a bit line bar are disclosed. ...	01/19/2010
7623368	Non-volatile semiconductor memory based on enhanced gate oxide breakdown A semiconductor memory structure based on gate oxide break down is constructed in a deep N-well. Thus, the electrical field over the programmable element during the transient procedure of gate oxide break down can be controlled to achieve the best memory programming...	11/24/2009
7589990	Semiconductor ROM device and manufacturing method thereof The present invention provides a new semiconductor Read-Only Memory, ROM, which stores more than one bit per cell. The potential of multiple threshold voltages combined with the potential multiple ratios of device channel width and length makes an ROM cell store mul...	09/15/2009
7567450	Low power ROM A low power ROM includes a plurality of ROM core groups coupled between a plurality of word lines and bit lines, a word line decoder for selecting a desired word line of the plurality of word lines, a column decoder for selecting a desired bit line of the plurality ...	07/28/2009
7561457	Select transistor using buried bit line from core A semiconductor device includes a core memory array and a periphery area. The core memory array area includes a group of memory cells. The periphery area includes a group of select transistors. The select transistors are formed at substantially the same pitch as the...	07/14/2009
7471541	Memory transistor gate oxide stress release and improved reliability Methods and apparatus for decreasing oxide stress and increasing reliability of memory transistors are disclosed. Duration and frequency of exposure of memory transistor gates to read signals are significantly reduced. In some embodiments, after a short read cycle, ...	12/30/2008
7471540	Non-volatile semiconductor memory based on enhanced gate oxide breakdown A semiconductor memory structure based on gate oxide break down is constructed in a deep N-well. Thus, the electrical field over the programmable element during the transient procedure of gate oxide break down can be controlled to achieve the best memory programming...	12/30/2008
7447054	NBTI-resilient memory cells with NAND gates An NBTI-resilient memory cell is made up of a ring of multiple NAND gates. The NAND gates are arranged such that one of the NAND gates has a “0” in its output, while the remaining NAND gates have a “1” in their outputs. PMOS transistors within the memory cel...	11/04/2008
7443706	High-performance memory and related method In memory array of a memory circuit, a discharging module and an auxiliary module are disposed on each column line. While accessing an objective memory unit on a column line of the memory, the memory unit discharges the corresponding row line of the objective memory...	10/28/2008
7436690	Flat cell read only memory using common contacts for bit lines and virtual ground lines In a flat cell read only memory, two bit lines or two virtual ground lines share a common contact such that the contact is slightly adjustable in its location for inserting a local metal word line without increasing the layout area to improve the reading speed of th...	10/14/2008
7414909	Nonvolatile semiconductor memory There is provided a high-density mask ROM operable at a high speed. With the mask ROM, respective source lines are disposed so as to be shared by memory cells in respective columns adjacent to each other, and bit lines are disposed so as to correspond to the respect...	08/19/2008
7411808	Method for reading ROM cell A method for reading data stored in a multiple bit memory cell, the memory cell comprising a switch located within an array of switches arranged in columns and rows, each switch having a control node and first and second switched nodes between which the flow of curr...	08/12/2008
7408826	Semiconductor memory device A semiconductor memory device that includes a memory cell array having a plurality of memory cells that are connected between a bit line pair, which transfers data to the bit line pair, a precharge circuit for precharging the bit line pair to a precharge voltage lev...	08/05/2008
7408806	Memory array architecture for a memory device and method of operating the memory array architecture A high integration memory array architecture of the present invention includes a memory cell array including memory cells arranged in a predetermined configuration, and selection transistors having different threshold voltages so as to select a memory string of the ...	08/05/2008
7379318	Semiconductor integrated circuit device and method for manufacturing the same A semiconductor integrated circuit device includes a semiconductor substrate and a ROM region, an SRAM region and a peripheral circuit region which are formed on the semiconductor substrate. Further, a column switch region is provided adjacent to the ROM region. MOS...	05/27/2008
7376000	Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets Structures and methods of adding metal-to-metal capacitors to static memory cells to reduce susceptibility to SEUs. The addition of metal-to-metal capacitors is particularly suited to programmable logic devices (PLDs), because of the relatively large area required t...	05/20/2008
7372763	Memory with spatially encoded data storage In some embodiments, the invention provides a chip with at least one memory circuit that comprises a majority voter circuit with first and second digitally controlled variable delay elements. The first delay element is controlled by data bits that are to be written ...	05/13/2008
7372716	Memory having CBRAM memory cells and method A memory cell arrangement has a plurality of memory cells of the CBRAM type and a programming apparatus, the memory cells being arranged along bit lines and each bit line having a programming apparatus. The invention provides for the programming apparatus to compris...	05/13/2008
7366013	Single level cell programming in a multiple level cell non-volatile memory device A multiple level cell memory array has an area that can be programmed as single level cells. The cells to be programmed are initially programmed with the desire data into either the least significant or most significant bit of the cell. A second programming operatio...	04/29/2008
7359226	Transistor, memory cell array and method for forming and operating a memory device A substrate forming an array of vertical transistor cells for selecting one of a plurality of memory cells and wherein each memory cell couples a transistor to a bit line via a memory element and is addressable by selecting two word lines and a bit line is disclosed...	04/15/2008
7359230	Nonvolatile memory device Provided is a nonvolatile memory device including: a storage element; a switching element electrically connected to the storage element; and a plurality of lead wirings electrically connected to the switching element, all of which are arranged on a substrate having ...	04/15/2008
7355890	Content addressable memory (CAM) devices having NAND-type compare circuits Content addressable memory (CAM) devices have CAM cells therein that are electrically coupled to a NAND-type compare circuit. This NAND-type compare circuit is responsive to a first operand (K) containing true and complementary bits of an applied search key and a se...	04/08/2008

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Class 365/104 - Transistors