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"That the automobile has practically reached the limit of its development is suggested by the fact that during the past year no improvements of a radical nature have been introduced."
Scientific American ; Jan. 2 edition, 1909
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| Number | Title | Issue Date |
| 7193999 | Reception system for replacing transport packets A reception system has a receiving section which receives a transport stream transmitted from a transmission system that produces and transmits the transport stream, the transport stream being produced by multiplexing compression coded contents of a program, and ele... | 03/20/2007 |
| 7190551 | Composite magnetic head and process for producing the same A composite magnetic head comprising a DC-erasing head, which is slidably contact with a driving magnetic tape, and which DC-erases a servo band of the magnetic tape in such a manner that the direction of the magnetization of the servo band the servo band is directe... | 03/13/2007 |
| 7190718 | Method and apparatus for determining a receiver sampling phase for use in diagnosing a channel An apparatus for processing a received signal includes an analog-to-digital converter (ADC) configured to produce a sampled signal from a received signal using a candidate sampling phase. An adaptive filter includes adaptive filter coefficients and is configured to ... | 03/13/2007 |
| 7187743 | Frequency error correction in a communication system A technique for performing a frequency error correction process is provided that may be used in receivers of wireless local area network systems. The technique comprises a three-phase process generating a frequency approximation value based on a frequency error esti... | 03/06/2007 |
| 7187142 | Motor drive with velocity noise filter A drive unit for controlling a motor includes a position feedback device and a velocity noise filter. The position feedback device is operable to generate a position signal relating to a position of the motor. The velocity noise filter is coupled to the position fee... | 03/06/2007 |
| 7184505 | Data synchronizing signal detecting device A data sync signal detecting device for detecting a sync signal having sync signal detection errors. The detecting device applies the output data of a most-likelihood decoder to shift register bit cells. The data is sequentially shifted and held in the bit cells of ... | 02/27/2007 |
| 7184230 | System and method for processing track identifier errors to mitigate head instability in data storage devices A system and method for processing track identifier errors to mitigate head instability in data storage devices is disclosed. The system and method includes computing a track id differential between an expected track id and a received track id, encoding the expected... | 02/27/2007 |
| 7184233 | Dual source tracking servo systems and associated methods In one example, a dual source tracking servo system includes a head assembly having a data transducer, a primary position detector for sensing the position of a magnetically stored data track, and a secondary position detector for sensing the position of a fixed ref... | 02/27/2007 |
| 7184234 | Compensation for jitter in servo signal within data storage device For compensating for jitter within a data storage device in real time, a jitter amount is determined from timings of servo signals for sectors of the data storage device. A timing of a servo gate pulse is adjusted for accessing another sector depending on the jitter... | 02/27/2007 |
| 7184486 | LDPC encoder and decoder and method thereof A method of decoding low-density parity-check codes comprises a first step that includes calculating └└rRml, for each parity check equation, at iteration i−1, in response to a third step. A second step includes decision aided equalizing, at iteratio... | 02/27/2007 |
| 7180693 | Method and apparatus for maximum likelihood detection of data employing interpolation with compensation of signal asymmetry A method and apparatus are disclosed for detecting data, such as a sample sequence read from a recording channel. Interpolation techniques are employed to generate one or more interpolated sample sequences from the data. Each interpolated sample sequence has a diffe... | 02/20/2007 |
| 7181584 | Dynamic command and/or address mirroring system and method for memory modules A memory module includes a memory hub that couples signals to memory devices mounted on opposite first and second surfaces of a memory module substrate. The memory devices are mounted in mirrored configuration with mirrored terminals of memory devices on opposite su... | 02/20/2007 |
| 7177114 | Apparatus, system, and method for the velocity proportional clocking of time base servo tape storage devices An apparatus, system, and method are disclosed for the velocity proportional clocking of time base servo tape storage devices. The apparatus, system, and method allow the velocity of time base servo tape storage devices to be adjusted and maintained by adjusting the... | 02/13/2007 |
| 7177105 | Disk synchronous write An apparatus, method, and system for writing data to a hard disk drive synchronous with an apparent disk speed. The apparatus, method, and system has a phase-locked loop (PLL) to generate am output clock signal, wherein a clock interpolator responsive to phase rotat... | 02/13/2007 |
| 7174445 | Flash memory card with enhanced operating mode detection and user-friendly interfacing system An interfacing system facilitating user-friendly connectivity in a selected operating mode between a host computer system and a flash memory card. The interfacing system includes an interface device and a flash memory card. The interfacing system features significan... | 02/06/2007 |
| 7173786 | Magnetic disk drive apparatus and method for compensating characteristics of magnetic disk drive apparatus A magnetic disk drive apparatus includes a magnetic disk with a data region, a magnetic head located in a region of the magnetic disk other than the data region or outside of the magnetic disk before startup of the magnetic disk and loaded on the data region after t... | 02/06/2007 |
| 7173551 | Increasing data throughput in optical fiber transmission systems Data throughput rates are increased in an optical fiber communication system without requiring replacement of the existing optical fiber in a link. Channel throughput is increased by upgrading the components and circuitry in the head and terminal of an optical fiber... | 02/06/2007 |
| 7174409 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 02/06/2007 |
| 7170703 | Flaw detection in disk drive using significant samples of data pattern stored on disk Detecting flaws in a disk drive includes sampling a read signal provided by reading a data pattern from a disk to obtain samples, obtaining significant samples from the samples, deriving a value from the significant samples, and reporting a flaw if a comparison betw... | 01/30/2007 |
| 7167535 | Circuit sharing for frequency and phase error correction A WLAN (Wireless Local Area Network) receiver with a synchronization unit is provided, wherein the synchronization unit comprises a frequency error correction unit configured to perform a frequency error correction process, a phase error correction unit configured t... | 01/23/2007 |
| 7167333 | Method and apparatus for writing and reading servo information written in a spiral fashion A method and apparatus for writing spiral servo information onto one or more disk surfaces at a variable velocity using a servo track writer (STW) is provided. In one embodiment, a variable velocity profile is chosen so that spiral crossing angles across the disk su... | 01/23/2007 |
| 7167328 | Synchronizing an asynchronously detected servo signal to synchronous servo demodulation A first set of data is detected in a signal having synchronous samples and interpolated samples, wherein the first set of data is detected asynchronously as corresponding to one of the samples. A time to transmit a data-found signal is determined based on an offset ... | 01/23/2007 |
| 7167327 | Integrated circuit and method for remodulating bits and hard disk drive incorporating the same A remodulator embodied in an integrated circuit (IC), a method for remodulating bits and a controller and disk drive incorporating the IC or the method. In one embodiment, the IC includes: (1) a remodulator that processes incoming bits to yield remodulated outgoing ... | 01/23/2007 |
| 7164635 | Method of estimation parameter adaptability adjustment of an optical storage device A method of estimation parameter adaptability adjustment of an optical storage device. The method determines an estimation parameter according to a current data recording location of the optical storage device to estimate a channel bit rate. The method includes prov... | 01/16/2007 |
| 7161754 | Servo pattern writing method and magnetic disk drive for carrying out the same A servo pattern writing method of writing a servo pattern for the positioning control of a magnetic head on a magnetic disk comprises changing the rotating speed of the magnetic disk with the magnetic head positioned at one or more proper radial positions with respe... | 01/09/2007 |
| 7161759 | Self servo writing using servo burst edge errors for compound error correction The present invention provides self-servo writing by which self-propagated servo pattern track shape errors are reduced or eliminated. The method includes providing first servo bursts on a first track, measuring edge errors of the first servo bursts, and self-servo ... | 01/09/2007 |
| 7159092 | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to store the signals responsive to the clock. A phase command for each digit... | 01/02/2007 |
| 7158601 | Clock data recovery method and circuit for network communication Embodiments of the present invention relate to a method for recovering the clock and data signals in a transmitted data signal In a computer network. The method comprises accessing a transmitted a data signal at a receiver in the network, locking the receiver on a d... | 01/02/2007 |
| 7158328 | Multi-phase acceleration of a data storage disc A disc drive having a multi-phase acceleration procedure is disclosed. The multi-phase acceleration procedure accelerates a data storage disc in the disc drive from an initial rotational velocity to a final rotational velocity. As the disc reaches the final rotation... | 01/02/2007 |
| 7158565 | Waveform equalizer and shift register In a tap 1 in a shift register of a waveform equalizer, data of an input signal is stored in a data storing FF 111. A tap coefficient computing unit 114 calculates a tap coefficient, which is stored in a tap coefficient storing FF 112 and... | 01/02/2007 |
| 7155559 | Flash memory architecture with separate storage of overhead and user data A flash memory system segregates overhead data from user data so that overhead data may be addressed, programmed and erased independently from user data. The non-volatile memory medium of a flash memory system is mapped into a plurality of separately addressable mem... | 12/26/2006 |
| 7154424 | Digital equalization apparatus A digital equalization apparatus is provided with an analog low pass filter for removing a high-frequency component from an input analog signal, a non-linear analog to digital (A/D) converter for non-linearly sampling the analog signal to output a digital signal, an... | 12/26/2006 |
| 7152800 | Preamplifier system having programmable resistance A biasing scheme is disclosed that helps reduce current noise in an associated device, such as, for example, a magneto-resistive device. The biasing scheme provides for setting a resistance path in a preamplifier, which is operative to energize the associated device... | 12/26/2006 |
| 7151707 | Memory device and method having data path with multiple prefetch I/O configurations A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel t... | 12/19/2006 |
| 7149044 | Methods, apparatus and computer program products for writing tracks on a disk based on an available stroke Track pitch for writing tracks on a disk is determined based on an available stroke across the disk. The available stroke is identified by searching across the disk for where information can be written and read. The track pitch is determined for writing tracks on th... | 12/12/2006 |
| 7149256 | Multilevel pulse position modulation for efficient fiber optic communication Decreasing the average transmitted power in an optical fiber communication channel using multilevel amplitude modulation in conjunction with Pulse Position Modulation (PPM). This multilevel PPM method does not entail any tradeoff between decreased power per channel ... | 12/12/2006 |
| 7145373 | Frequency-controlled DLL bias A system for controlling bias of a delay-locked loop includes a peak detector and a comparator in the form of a differential amplifier. The peak detector detects the amplitude of a signal output from the DLL, and the comparator compares the DLL output signal amplitu... | 12/05/2006 |
| 7145744 | Reducing spiral write time and clock track drift while writing spiral reference patterns to a disk of a disk drive Disclosed is a method for reducing spiral write time and clock reference drift while writing spiral reference patterns on a disk of a disk drive. The method includes: controlling a radial location of a head for writing a first band of tracks near one of an outer dia... | 12/05/2006 |
| 7142622 | Multiplying phase detector for use in a random data locked loop architecture A multiplying phase detector includes a 1st multiplier, a 2nd multiplier and a phase error generation module. The 1st multiplier is operably coupled to multiple an incoming data stream, which is a random data pattern, with a 1st... | 11/28/2006 |
| 7142621 | Method and circuit for recovering a data signal from a stream of binary data There is disclosed a data recovery (DR) circuit including an over sampling (OS) circuit, a transition detection (TD) circuit and a sample selection/data alignment (SSDA) circuit. A multiphase clock generating circuit delivering n phases is coupled to each of these c... | 11/28/2006 |
