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| Number | Title | Issue Date |
| RE41399 | Technique to stabilize the chrominance subcarrier generation in a line-locked digital video system A technique to stabilize subcarrier generation in a line-locked digital video system, caused by simultaneous locking of the genlock device causing continuous changing of a shared clock signal, by calculating a time shift occurring in an output waveform, converting t... | 06/29/2010 |
| 7425991 | System and method for determining video subcarrier phase A system and method for determining phase of a subcarrier (e.g., a jittering video subcarrier). Various aspects of the present invention may comprise determining at least one weighting factor based, at least in part, on a subcarrier synchronization signal (e.g., a v... | 09/16/2008 |
| 7391472 | System and method for adaptive color burst phase correction We describe and claim an adaptive color burst phase correction system and method. The adaptive color burst phase correction system includes a signal detector to extract a color burst from a video signal, the color burst including a phase and an amplitude, an adaptiv... | 06/24/2008 |
| 7339628 | Method and apparatus to improve decoding of composite video signals Video decoder systems in which both the analog-to-digital converter and the composite decoder are driven by the stable sample clock, such as a crystal source. The outputs of the composite decoder are provided to a source rate converter, having an output that is prov... | 03/04/2008 |
| 7336748 | DDS circuit with arbitrary frequency control clock A test system using direct digital synthesis for generation of a spectrally pure, agile clock. The clock is used in analog and digital instruments in automatic test system. A DDS circuit is synchronized to the tester system clock because it is clocked by a DDS clock... | 02/26/2008 |
| 7330217 | Chroma phase error correction circuitry and methods and systems utilizing the same Chrominance phase error correction circuitry includes a demodulator for demodulating a received video color burst signal into first and second demodulated signals and signal generation circuitry for providing to the demodulator a demodulating signal for demodulating... | 02/12/2008 |
| 7321398 | Digital windowing for video sync separation A processing circuit for a sync signal includes a trial circuit and a windowing circuit. The trial circuit includes a counter that generates a count value proportional to the duration between successive sync pulses. When the count value reaches a trial sync spacing ... | 01/22/2008 |
| 7321397 | Composite color frame identifier system and method A color frame identifier circuit generates a pseudo-subcarrier signal and compares the pseudo-subcarrier signal to a sliced color burst of at least one selected line in a video frame. Based on this comparison, a processing circuit determines the color frame. ... | 01/22/2008 |
| 7319492 | Open loop subcarrier synchronization system A system and method for synchronizing signals having respective sub-carriers in a signal processing system. Various aspects of the present invention may comprise method steps and structure that receive a sampled signal with an associated sub-carrier. Various aspects... | 01/15/2008 |
| 7315661 | Directional interpolation method using DCT information and related device The invention provides a method for interpolating a pixel within an image. The image has a plurality of pixels arranged in a matrix format. The method includes detecting if there is an edge in a block of the image according to a Discrete Cosine Transform (DCT) data ... | 01/01/2008 |
| 7298916 | Image signal processing apparatus and method When performing A/D conversion on image signals, when reducing noise that is caused by jitter by adjusting the phase of the sampling clocks, even if the input waveform has considerable waveform distortion such as a triangular wave, it is possible to reliably reduce ... | 11/20/2007 |
| 7277134 | Chrominance signal demodulation apparatus An NTSC system chrominance signal demodulation apparatus is provided with a clock timing change circuit for burst-locking an input signal under the state where the phase is shifted by 90 degrees for every line, and phase axis rotation circuits for performing phase a... | 10/02/2007 |
| 7277133 | Adjusting pixel clock A pixel clock frequency is adjusted in response to periodically monitoring the relative positions between a video signal to be displayed and a video signal captured. Image shear of the display signal may be avoided quickly. Adjustments are made to the color burst si... | 10/02/2007 |
| 7268825 | Digital synchronizing generator A sync generator (genlock) (10) for frequency and phase locking an incoming video signal to a system clock (12) includes a digitizer (16, 22) for digitizing the incoming video signal to yield a digitized color sub-carrier burst component. A nume... | 09/11/2007 |
| 7239341 | Vector waveform rotation device A vector waveform rotation device (60) for rotating a vector waveform displayed on a vector comprises rotation amount setting means (5′) for holding a rotation amount α, and means (6′) for inputting a first color difference signal (B-Y sign... | 07/03/2007 |
| 7230615 | Method and apparatus for coordinating horizontal and vertical synchronization signals In a signal coordinating method and apparatus, a pulse generating circuit receives a VSYNC signal and generates a plurality of critical pulses that define critical time periods from fields can control edges of the VSYNC signal. A determining circuit receives an HSYN... | 06/12/2007 |
| 7224407 | Color demodulation device, color demodulation method and image display device A color demodualation device having an AD converter, a phase signal generator, a burst data generator and a multiplier. The AD converter produces digital samples of chrominance signal at a frequency four times a color subcarrier frequency, and the phase signal gener... | 05/29/2007 |
| 7202893 | Method and apparatus for the display of still images from image files An apparatus for displaying digital image files on a standard display device such as a television set is provided in the form of a set-top box. The box includes an integrated circuit and memory buffer for computing an image from a file, a second memory buffer for st... | 04/10/2007 |
| 7190407 | System, method and apparatus for sandcastle signal generation in a television signal processing device A system, method and apparatus are provided for generating 98 a sandcastle signal in a television signal receiver 90, and utilizing the sandcastle signal during television signal processing. In one form, the sandcastle signal is generated by subtractin... | 03/13/2007 |
| 7167208 | Digital broadcasting receiver and method for compensating color reproduction error of the same Digital broadcasting receiver, and method for compensating a color reproduction error therein, the digital broadcasting receiver including a channel decoder, a TP part for demultiplexing a TP stream from the channel decoder for being provided with a PCR (Program Clo... | 01/23/2007 |
| 7136109 | Self-adjusting pixel clock and method therefor A pixel clock generating circuit is provided in which a digital circuit generates a first signal corresponding to the relative frequency of the pixel clock as compared with a predetermined desired pixel clock frequency. An analog circuit is electrically coupled to t... | 11/14/2006 |
| 7092042 | Broadcasting receiver A PLL circuit compares a PCR with the output frequency of a voltage controlled oscillator (VCO), and returns a voltage value which is the result of the comparison to the VCO, so that a reference clock corresponding to the PCR is outputted from the VCO. A switch supp... | 08/15/2006 |
| 7080169 | Receiving data from interleaved multiple concurrent transactions in a FIFO memory having programmable buffer zones A FIFO memory receives data transfer requests before data is stored in the FIFO memory. Multiple concurrent data transfers, delivered to the FIFO memory as interleaved multiple concurrent transactions, can be accommodated by the FIFO memory (i.e., multiplexing betwe... | 07/18/2006 |
| 7065028 | Method and device for generating a clock signal that is coupled to a reference signal In order to generate a clock signal (fT1) that is coupled to a reference signal (FBAS), especially to an analog video signal, a free-running clock pulse (fT1) is generated from a high-frequency clock pulse (f0) and the reference sign... | 06/20/2006 |
| 7061541 | Apparatus and method for compensating a color carrier of an image signal An apparatus to compensate a color carrier in an image processing system to convert an input analog image signal into a digital image signal includes a detector, a phase-locked loop unit, a difference detector, and a color signal processor. The detector detects a fr... | 06/13/2006 |
| 7050097 | Method and apparatus for the display of still images from image files An apparatus for displaying digital image files on a standard display device such as a television set is provided in the form of a set-top box. The box includes an integrated circuit and memory buffer for computing an image from a file, a second memory buffer for st... | 05/23/2006 |
| 6947095 | Broadcast data receiver and method of use thereof A broadcast data receiver (BDR) is provided and a method of using the BDR for the production of a pseudo stable reference control for the reliable generation of composite video signals. The BDR receives video, audio and/or auxiliary data from a broadcaster can store... | 09/20/2005 |
| 6947060 | Image forming apparatus, electron beam apparatus, modulation circuit, and image-forming apparatus driving method An image forming apparatus which performs pulsewidth modulation with a pulsewidth set by counting a clock. Especially, for grayscale level correction by setting the frequency of the clock, the periodic clock is counted, and an output pattern is changed in accordance... | 09/20/2005 |
| 6943844 | Adjusting pixel clock A pixel clock frequency is adjusted in response to periodically monitoring the relative positions between a video signal to be displayed and a video signal captured. Image shear of the display signal may be avoided quickly. Adjustments are made to the color burst si... | 09/13/2005 |
| 6928036 | Harmonic correction in phase-locked loops Correction for harmonic disturbances on rotating storage media in a phase-locked loop. The effects of harmonic disturbances in a phase-locked loop are reduced by employing harmonic correction. Harmonic correction may be present in the loop at all times, or may be sw... | 08/09/2005 |
| 6914639 | Combination tuner capable of receiving television signal and FM signal A combination tuner includes a switching circuit having three transistors which are selectively turned on and off so that one of a television signal received by a first signal receiving unit using an external antenna that is a high sensitivity antenna, an FM signal ... | 07/05/2005 |
| 6912012 | Video decoder having lock algorithm that distinguishes between a noisy television signal input and a video recorder signal A phase-locked loop is provided which is operable to lock the sampling clock (pixel clock) to the incoming horizontal sync pulse contained within composite video information. Given the input signal is a VCR signal or a normal noise-free signal, there exists two mode... | 06/28/2005 |
| 6911863 | Integrated DVB filter A filter for processing frequency signals, preferably received, particularly digital television signals is described, which filter comprises a Chebyshev filter (11, 12), a subsequent all-pass filter (13) and a control device (14 to 20) fo... | 06/28/2005 |
| 6839092 | Feed forward error correction in video decoder In accordance with an embodiment of the present invention a microprocessor in the horizontal phased lock loop reads the horizontal timing with respect to the sync input and provides an increment inch to the horizontal discrete time oscillator to make corr... | 01/04/2005 |
| 6833875 | Multi-standard video decoder A video decoder for decoding a composite video signal. The decoder includes an analog-to-digital converter (ADC), an input resampler, and a Y/C separator, all coupled in series. The ADC receives and digitizes the composite video signal to generate ADC samples. The i... | 12/21/2004 |
| 6826247 | Digital phase lock loop A system includes a digital phase lock loop (PLL) constructed from an all digital circuit implementation and standard cell construction. The digital PLL includes a digital frequency synthesizer and a digital phase detector. The digital frequency synthesizer includes... | 11/30/2004 |
| 6753924 | Oscillation signal processing apparatus, television apparatus and oscillation signal processing control method In a conventional construction to obtain a reference signal for a tuner and a subcarrier for color difference signal demodulation by only one quartz oscillator, the reference signal is unstable due to a PLL operation for oscillation of the subcarrier, which causes t... | 06/22/2004 |
| 6741289 | Technique to stabilize the chrominance subcarrier generation in a line-locked digital video system A technique to stabilize subcarrier generation in a line-locked digital video system, caused by simultaneous locking of the genlock device causing continuous changing of a shared clock signal, by calculating a time shift occurring in an output waveform, converting t... | 05/25/2004 |
| 6538702 | Digital color signal reproducing circuit A color signal reproducing circuit having A/D converter 101, sync separator 102, YC separator 103, gain controller 105, multipliers 106 and 107, low-pass filters 108 and 109, burst-period cumulative adders 110 and 111, SINCOS generator 112, clock generato... | 03/25/2003 |
| 6429901 | PLL circuit and phase lock detector A PLL circuit which outputs an oscillation clock signal synchronous with a reference clock includes a phase lock detector for detecting if the oscillation lock signal is synchronous with the reference clock. If the phase lock detector detects a phase diff... | 08/06/2002 |
