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Dennis Gabor, British physicist
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| Number | Title | Issue Date |
| 6628292 | Creating page coherency and improved bank sequencing in a memory access command stream A buffer facilitates reordering of incoming memory access commands so that the memory access commands may be associated automatically according to their row/bank addresses. The storage capacity in the buffer may be dynamically allocated among groups as ne... | 09/30/2003 |
| 6608626 | Hardware rotation of an image on a computer display An address generator (FIG. 6) of a display controller (16) includes an adder (62) that repetitively adds an image-row-offset value to the address generator's address output so that data sequentially fetched from a refresh memory (18) to refresh a display ... | 08/19/2003 |
| 6577318 | Integrated circuit device and display device with the same An integrated circuit device includes a first memory unit and a conversion part for converting the parallel data read from the first memory unit into serial data. The integrated circuit device also includes a second memory unit that can write and read the... | 06/10/2003 |
| 6570568 | System and method for the coordinated simplification of surface and wire-frame descriptions of a geometric model A system simplifies a geometric model to accelerate the rendering of the geometric model. A surface description of the geometric model is stored in one or more of the system memories. A wire-frame description of the geometric model is also stored. A surfa... | 05/27/2003 |
| 6567719 | Method and apparatus for creating an improved image on a photomask by negatively and positively overscanning the boundaries of an image pattern at inside corner locations An method for creating an image on a photosensitive material with enhanced inside corner resolution using a raster scan exposure system. The photosensitive material may comprise a layer of an unexposed photomask. An energy beam scan is extended by one or ... | 05/20/2003 |
| 6486884 | Apparatus for accessing memory in a video system and method thereof A method and apparatus for storing sequential data words associated with a block of data in a non-linear manner within the data block is taught such that any row or column associated with the data block may be accessed using a burst access. A row, or colu... | 11/26/2002 |
| 6356988 | Memory access system, address converter, and address conversion method capable of reducing a memory access time On storing two-dimensional arrangement data into a memory (1) having banks, 2n in number, each of which is individually assigned with a bank number B and includes row addresses identified by row address numbers A, an address converter (3) calcu... | 03/12/2002 |
| 6307649 | Mountable scanning device and computer monitor including same A scanner includes a housing defining a front housing opening and, in some instances, a rear housing opening and a movable scanner module located within the housing. The scanner with front and rear housing openings can be mounted on, for example, a comput... | 10/23/2001 |
| 6307588 | Method and apparatus for address expansion in a parallel image processing memory A method and apparatus for image processing provides a memory having a plurality of individual parallel buffers constructed from random access memories (RAMs) for storing data related to a group of image pixels. The buffers each store a parallel, identica... | 10/23/2001 |
| 6304266 | Method and apparatus for volume rendering A volume rendering process is disclosed. Data including a plurality of voxels are recorded. Each voxel includes an opacity-adjusted value representative of a value of a parameter at a location within the volume adjusted by applying an opacity curve to the... | 10/16/2001 |
| 6301649 | Semiconductor circuit with address translation circuit that enables quick serial access in row or column directions In a semiconductor memory, memory banks each having memory cells are arranged in X and Y directions. Each of the memory banks include a Y decoder for selecting Y-direction addresses of the memory cells and an X decoder for selecting X-direction addresses ... | 10/09/2001 |
| 6297831 | Image generator using display memory A graphics system is used with a display capable of displaying a frame of an image via a sequence of scan lines. The graphics system has a memory and an image generator. The image generator is connected to store the data associated with some of the scan l... | 10/02/2001 |
| 6262751 | Hardware rotation of an image on a computer display An address generator (FIG. 6) of a display controller (16) includes an adder (62) that repetitively adds an image-row-offset value to the address generator's address output so that data sequentially fetched from a refresh memory (18) to refresh a display ... | 07/17/2001 |
| 6233658 | Memory write and read control A memory control system includes a frame memory divided into N image memories. Serial input image data are sequentially written into the N image memories in rotation. Then, image data is concurrently read from each of the N image memories depending on a d... | 05/15/2001 |
| 6226016 | Display apparatus and method capable of rotating an image by 180 degrees A central processing unit (310) in a display system carries pixel-value signals and software-address signals representing the locations of the pixels whose values the pixel-value signals represent. An address-translation circuit (420) converts those softw... | 05/01/2001 |
| 6201529 | Liquid crystal display apparatus and method of driving the same An electrically controlled birifringence type liquid crystal display panel has a pictograph (picto) display area and character display areas. Character codes are stored in a DDRAM and color attribute data indicating the display colors of characters are st... | 03/13/2001 |
| 6181354 | Image generator using display memory A graphics system is used with a display capable of displaying a frame of an image via a sequence of scan lines. The graphics system has a memory and an image generator. The image generator is connected to store the data associated with some of the scan l... | 01/30/2001 |
| 6104416 | Tiling in picture memory mapping to minimize memory bandwidth in compression and decompression of data sequences A method of storing a picture in a memory such that the latency of the memory can be reduced when retrieving a picture from the memory to be displayed while still reducing the bandwidth when retrieving an array portion of the picture from the memory, and ... | 08/15/2000 |
| 6075545 | Methods and apparatus for storing, accessing and processing images through the use of row and column pointers Methods and apparatus for storing, accessing, and processing information representing images through the use of row and column pointers are described. By manipulating and/or generating new sets of row and column pointers, many image processing operations ... | 06/13/2000 |
| 6064407 | Method and apparatus for tiling a block of image data A method and apparatus for tiling a block of image data is accomplished by first receiving a set of parameters that describe the block of image data. An address is determined based on the set of parameters, and the address is translated to a corresponding... | 05/16/2000 |
| 6040844 | Apparatus and method for storing and accessing picture generation data A system for mapping texture data at high speed with flexibility to different applications wherein texture data is sent to a memory interface (MEMIF) thorough a digital differential analyzer (DDA) and a texture mapping unit (TMAP) and loaded to free areas... | 03/21/2000 |
| 6005592 | Image processing apparatus having improved memory access for high speed 3-dimensional image processing An image processing apparatus suitable for three-dimensional high speed image processing can be realized by improving the memory address control and the access method, that is, by improving the data transfer speed between the image memory and the other un... | 12/21/1999 |
| 5956049 | Hardware that rotates an image for portrait-oriented display A system for translating a portrait-oriented software address to a portrait-oriented yet landscape-configured display address. The system includes a central processing unit (CPU), a display device and an address translation system. The CPU generates a sof... | 09/21/1999 |
| 5933159 | Memory system for processing digital video signal A memory system for processing a digital video signal capable of accessing data in block units includes a detector circuit discriminating whether the memory system is in a reading/writing operation in one of an integer pel mode and a half pel mode. A cont... | 08/03/1999 |
| 5923340 | Process of processing graphics data The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored... | 07/13/1999 |
| 5854641 | Method and apparatus for display image rotation A method and an apparatus for rotating images on a computer system is disclosed. The system includes a processor for accessing an image frame buffer using a set of CPU addresses, a memory for storing the frame buffer, a controller for directing the pixel ... | 12/29/1998 |
| 5829007 | Technique for implementing a swing buffer in a memory array A RAM implementation of asynchronous swing buffering is provided in which two buffers are operated asynchronously; one is written while the other is read. Accordingly, this allows for a data stream having a fast rate of through-put to be resynchronized to... | 10/27/1998 |
| 5815169 | Frame memory device for graphics allowing simultaneous selection of adjacent horizontal and vertical addresses A frame memory device for graphics includes a frame memory made up of a pair of memories and a memory controller for controlling the frame memory and is able to smoothly access the frame memory and is improved in its rendering speed. Each memory is logica... | 09/29/1998 |
| 5717441 | Picture data memory with high access efficiency in detecting motion vectors, a motion vector detection circuit provided with the picture data memory, and an address conversion circuit The address generation unit 166 generates a write address for each picture data to be written in the frame memory 169. The memory control unit 165 writes picture data which have the same Y address and consecutive X addresses to the first bank and the seco... | 02/10/1998 |
| 5706480 | Memory device and method for processing digital video signal A memory device for processing a block of digital video signal data comprises a random block access (RBA) controller for generating a system control signal to thereby vary a size of the block, an address generator for receiving external address signals ac... | 01/06/1998 |
| 5703616 | Display driving device A display data memory which is provided in a segment driver for driving a liquid crystal display panel comprises a plurality of memories. Since the common Y address is provided to all the memories, one predetermined memory is selected when a predetermined... | 12/30/1997 |
| 5704059 | Method of write to graphic memory where memory cells designated by plurality of addresses selected simultaneously for one row address are written In a method of write to a graphic memory where memory cells designated by a plurality of addresses selected simultaneously for one ROW address, the present method of write includes a first step of dividing the area corresponding to the column addresses de... | 12/30/1997 |
| 5696947 | Two dimensional frame buffer memory interface system and method of operation thereof A two dimensional frame buffer memory interface structure is provided. The interface comprises a parallel data bus, a control signal bus, a data cache, and a controller. The parallel data bus transfers a set of pixel data in parallel to the data cache. Th... | 12/09/1997 |
| 5680591 | Method and apparatus for monitoring a row address strobe signal in a graphics controller A method and apparatus for integrating a row address strobe signal monitoring circuit in a graphics controller is described. The present invention includes an improved graphics controller comprising a bi-directional input/output pad and a row address stro... | 10/21/1997 |
| 5668979 | Storage of clipping plane data in successive bit planes of residual frame buffer memory A system and method for storing clipping, masking or stenciling plane data in an unused or residual portion of a frame buffer used with a graphics display. The clipping plane data corresponding to the pixels in the displayed portion of the frame buffer ar... | 09/16/1997 |
| 5664162 | Graphics accelerator with dual memory controllers A processor having two separate and relatively independent memory controllers to achieve a dual interface architecture. A first memory controller is coupled to the host interface for retrieving data and instructions and a second memory controller is coupl... | 09/02/1997 |
| 5631672 | Self-timed real-time data transfer in video-RAM A Video-RAM semiconductor memory device comprised of a RAM army having an address input for inputting row, column, and target addresses, and a serial access array having a serial output port. The Video-RAM has address/control logic which detects a stimulu... | 05/20/1997 |
| 5557734 | Cache burst architecture for parallel processing, such as for image processing A parallel processing system for processing data matrices, such as images, is disclosed. The system includes a plurality of processing units, organized in four blocks of eight processing units per processing chip, and external cache burst memory, wherein ... | 09/17/1996 |
| 5553229 | Row addressable graphics memory with flash fill A single-chip semiconductor memory device optimized for high performance flat-shaded polygon video systems consists of a RAM with flash fill circuitry whereby the Start and End addresses are specified for a given row; the data within this range are read, ... | 09/03/1996 |
| 5550961 | Image processing apparatus and method of controlling the same Texture mapping is performed on polygons at the same speed as a polygon drafting process without a texture cache, thereby reducing complexity without an increase in cost. An image memory is constituted in a double-buffer structure, and an address line, a ... | 08/27/1996 |
