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| Number | Title | Issue Date |
| 7272703 | Program controlled embedded-DRAM-DSP architecture and methods An efficient embedded-DRAM processor architecture and associated methods. In one exemplary embodiment, the architecture includes a DRAM array, a set of register files, set of functional units, and a data assembly unit. The data assembly unit includes a set of row-ad... | 09/18/2007 |
| 7205993 | Checkerboard buffer using two-dimensional buffer pages and using memory bank alternation Methods and apparatus for storing and retrieving data. In one implementation, a system includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least four memories, each having memory pages, data stored to at... | 04/17/2007 |
| 7164426 | Method and apparatus for generating texture A deferred graphics pipeline processor comprising a texture unit and a texture memory associated with the texture unit. The texture unit applies texture maps stored in the texture memory, to pixel fragments. The textures are MIP-mapped and comprise a series of textu... | 01/16/2007 |
| 7102646 | Demand-based memory system for graphics applications A memory system and methods of operating the same that drastically increase the efficiency in memory use and allocation in graphics systems. In a graphics system using a tiled architecture, instead of pre-allocating a fixed amount of memory for each tile, the invent... | 09/05/2006 |
| 7088369 | Checkerboard buffer using two-dimensional buffer pages and using bit-field addressing Methods and apparatus for storing and retrieving data. In one implementation, a system includes: a data source, providing data in a first order; a data destination, receiving data in a second order; memory devices having memory pages, data stored in parallel and ret... | 08/08/2006 |
| 7050032 | Ram-incorporated driver, and display unit and electronic equipment using the same The present invention provides a RAM-incorporated driver that enables the writing of moving-image data to a RAM simultaneously with the writing of still-image data to a RAM, at a reduced energy consumption. The RAM incorporated X-driver IC receives still-image data ... | 05/23/2006 |
| 7047373 | Memory control apparatus and method for controlling memory access capable of selecting desirable page mode In a memory control apparatus and a method for controlling memory access capable of selecting a desirable page mode, so as to reduce memory access time, a storage circuit receives threshold page hit ratios for each of a plurality of bus masters, and stores the thres... | 05/16/2006 |
| 7038692 | Method and apparatus for providing a vertex cache A method for caching data defining vertices of a polygon to be displayed by an input/output display device including the steps of providing an index by a vertex for which data is to be cached, storing data defining attributes of a polygon at a vertex in a cache unde... | 05/02/2006 |
| 7034791 | Digital video display employing minimal visual conveyance Select areas and specific pixels of a digital video display screen may be updated at video frame rate while other areas or pixels are not updated at video frame rate. Further, select pixels may be updated more than once within the normal update timing of a single vi... | 04/25/2006 |
| 7030792 | Suppressing digital-to-analog converter (DAC) error A digital-to-analog converter (DAC) error suppression arrangement suppresses DAC error arising from mismatched elements contained in a DAC (640 and/or 645) that is part of a modulator (FIG. 6). A low pass averaging (LPA) index decoder 650... | 04/18/2006 |
| 7027061 | Raster engine with multiple color depth digital display interface An improved raster engine adapted to render video data from a frame buffer to one of a plurality of disparate displays is disclosed which comprises an integral bounded video signature analyzer, a hardware cursor apparatus supporting dual scanned displays, programmat... | 04/11/2006 |
| 6992674 | Checkerboard buffer using two-dimensional buffer pages and using state addressing Methods and apparatus for storing and retrieving data using two-dimensional arrays. In one implementation, a checkerboard buffer page system includes: a data source, providing data elements in a first order; a data destination, receiving data elements in a second or... | 01/31/2006 |
| 6972768 | Method and apparatus for rasterizing in a hierarchical tile order A method and apparatus for efficiently rasterizing graphics is provided. The method is intended to be used in combination with a frame buffer that provides fast tile-based addressing. Within this environment, frame buffer memory locations are organized into a tile h... | 12/06/2005 |
| 6965980 | Multi-sequence burst accessing for SDRAM Methods and apparatus for accessing memory locations in a memory device in different orders. In one implementation, a memory device includes: a memory array, including a plurality of memory locations divided into memory pages, where each memory location has a row ad... | 11/15/2005 |
| 6876400 | Apparatus and method for protecting a memory sharing signal control lines with other circuitry An apparatus such as a television signal receiver includes first and second circuit boards. The first circuit board includes a memory, and control circuitry for controlling at least one function of the apparatus. The second circuit board is operably coupled to the f... | 04/05/2005 |
| 6870578 | Apparatus and method for sharing signal control lines An apparatus such as a television signal receiver includes first and second circuit boards. The first circuit board includes a first device such as a memory, and control circuitry for controlling at least one function of the apparatus. The second circuit board is op... | 03/22/2005 |
| 6847370 | Planar byte memory organization with linear access A graphics memory architecture in which row addresses are permuted, in a basically tile-oriented storage architecture, so that fast parallel access is provided both by scanlines (for video operations) and also by tiles (for graphics operations). ... | 01/25/2005 |
| 6847410 | Picture data memory device with picture data input channels and picture data output channels A picture data memory device which can be used universally comprises a central picture data memory for storing picture data of a plurality of picture data input channels, in which case the stored picture data can additionally be read out via a plurality of picture d... | 01/25/2005 |
| 6833834 | Frame buffer organization and reordering A graphics system includes a frame buffer, a write address generator, and a pixel buffer. A burst of pixels received from the frame buffer may not be in display order. In one embodiment, a write address generator calculates a write address for each pixel in the burs... | 12/21/2004 |
| 6680737 | Z test and conditional merger of colliding pixels during batch building Frame buffer memory bandwidth is conserved by performing a depth comparison between colliding pixels at batch building time. If the incoming pixel fails the depth comparison, then it may be "tossed" and excluded from any batches currently under constructi... | 01/20/2004 |
| 6633298 | Creating column coherency for burst building in a memory access command stream A buffer facilitates reordering of memory access commands in a memory access command stream so as to create column coherencies that may be exploited with burst-mode memory cycles. A multi-column data storage buffer is provided. Storage control circuitry s... | 10/14/2003 |
| 6628292 | Creating page coherency and improved bank sequencing in a memory access command stream A buffer facilitates reordering of incoming memory access commands so that the memory access commands may be associated automatically according to their row/bank addresses. The storage capacity in the buffer may be dynamically allocated among groups as ne... | 09/30/2003 |
| 6559852 | Z test and conditional merger of colliding pixels during batch building Frame buffer memory bandwidth is conserved by performing a depth comparison between colliding pixels at batch building time. If the incoming pixel fails the depth comparison, then it may be "tossed" and excluded from any batches currently under constructi... | 05/06/2003 |
| 6542159 | Apparatus to control memory accesses in a video system and method thereof A method and apparatus for dynamic issuing of memory access instructions. In particular, a specific data access request that is about to be sent to a memory, such as a frame buffer, is dynamically chosen based upon pending requests within a pipeline. It i... | 04/01/2003 |
| 6249853 | GART and PTES defined by configuration registers A modular architecture for storing, addressing and retrieving graphics data from main memory instead of expensive local frame buffer memory. A graphic address remapping table (GART), defined in software, is used to remap virtual addresses falling within a... | 06/19/2001 |
| 6091428 | Frame buffer memory system for reducing page misses when rendering with color and Z buffers In a computer image generation system, a method for reducing page switches when rendering polygons to a color and Z-buffer using a memory subsystem with N banks of memory. The method is performed by first allocating the pages of a first memory subsystem (... | 07/18/2000 |
| 6078336 | Graphics memory system that utilizes look-ahead paging for reducing paging overhead The present invention provides a graphics memory system comprising at least one memory controller that utilizes a first-in-first-out (FIFO) memory architecture in combination with a look-head paging technique for paging a frame buffer memory having a mult... | 06/20/2000 |
| 6052134 | Memory controller and method for dynamic page management A computer is provided having a memory system supporting page mode accessing. A memory controller may be provided in a bus interface unit coupled between a CPU bus, and a mezzanine bus, or PCI bus. The memory controller includes logic that provides for dy... | 04/18/2000 |
| 6018354 | Method for accessing banks of DRAM This invention discloses a method for accessing Dynamic Random Access Memory (DRAM) to store and retrieve data words associated with a two dimensional image. The DRAM includes two separate banks, a first bank and a second bank. Each bank is capable of ope... | 01/25/2000 |
| 5982398 | Image processing device An image processing apparatus performs one of reading and writing of pixel data for a predetermined number of pixels at one access to a frame buffer which stores the pixel data, the frame buffer comprising a memory to which access in a page mode can be pe... | 11/09/1999 |
| 5852451 | Pixel reordering for improved texture mapping A system and method for reordering memory references for pixels to improved bandwidth and performance in texture mapping systems and other graphics systems by improving memory locality in conventional page-mode memory systems. Pixel memory references are ... | 12/22/1998 |
| 5796412 | Image data storing method and processing apparatus thereof An image data storing method and the processing apparatus thereof capable of improving the bandwidth of a data bus. According to the method, an image data of M pixels×N lines is stored in a field memory, which is for use in an image data processing appar... | 08/18/1998 |
| 5687357 | Register array for utilizing burst mode transfer on local bus Apparatus and a method by which an application program writing a series of commands to a single destination on an input/output bus increments the addresses to which the commands are addressed as the commands are written so that the commands may be transfe... | 11/11/1997 |
| 5642138 | Display control system using a different clock in the graphics mode from that in the text mode in accessing an image memory Depending on whether the display mode specified by a CPU is the graphics mode or the text mode, the access mode of an image memory is switched. In the text mode, a random access is executed in a single read cycle with the timing synchronizing a video cloc... | 06/24/1997 |
| 5612863 | Sorting sequential data prior to distribution over parallel processors in random access manner A data processing system comprises a plurality of processing elements being operative to process data and being coupled in parallel to a bus via a control means that governs data communication. The control means comprises a plurality of buffer means, and ... | 03/18/1997 |
| 5577193 | Multiple data registers and addressing technique therefore for block/flash writing main memory of a DRAM/VRAM A frame buffer construction and data storage technique for computer graphics display systems are presented employing a plurality of on-chip color registers. The plurality of on-chip color registers facilitate block writing and flash writing of multiple co... | 11/19/1996 |
| 5559952 | Display controller incorporating cache memory dedicated for VRAM A frame buffer cache is arranged to store part of image data in an image memory so that a CPU and a drawing processor can perform image data read/write operations by only accessing the frame buffer cache. Therefore, the image data read/write operations of... | 09/24/1996 |
| 5412777 | Display device having a built-in memory A timing generator 12' applies a control signal SC1 consisting of a row address strobe signal RAS1, a column address strobe signal CAS1 and a writing control signal WE1 to a control input C of a DRAM 31 while it also applies a control signal SC2 consistin... | 05/02/1995 |
| 5353402 | Computer graphics display system having combined bus and priority reading of video memory A display memory having a DRAM port and a serial port, a video controller including a host graphics controller having a bus port, a lookup table and a digital-to-analog converter for receiving lookup table data from the lookup table and converting it into... | 10/04/1994 |
| 5321809 | Categorized pixel variable buffering and processing for a graphics system A modified frame buffer and pixel variable read-modify-write method are described for a high performance computer graphics system. Pixel variables are initially classified as decision variables, intensity variables or decision/intensity variables. Only de... | 06/14/1994 |
