Did You Know...
...that the Band-Aid Bandage was invented by a Johnson & Johnson employee whose wife had cut herself? Earl Dickson's wife was rather accident prone, so he set out to develop a bandage that she could apply without help. He placed a small piece of gauze in the center of a small piece of surgical tape, and what we know today as the Band Aid bandage was born!
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| Number | Title | Issue Date |
| 7986327 | Systems for efficient retrieval from tiled memory surface to linear memory display Embodiments of the present invention set forth a technique for optimizing the on-chip data path between a memory controller and a display controller within a graphics processing unit (GPU). A row selection field and a sector mask are included within a memory access ... | 07/26/2011 |
| 7737986 | Methods and systems for tiling video or still image data The present disclosure describes methods and systems for tiling video or still image data. At least some preferred embodiments include a method for accessing data that includes partitioning a display of graphical data into a plurality of two-dimensional tiles; mappi... | 06/15/2010 |
| 7719541 | Method and apparatus for hardware rotation A method and apparatus for hardware rotation is described. In one embodiment, the invention is an apparatus. The apparatus includes a direct access address translation component. The apparatus also includes a frame buffer coupled to the direct access address transla... | 05/18/2010 |
| 7397477 | Memory system having multiple address allocation formats and method for use thereof A system and method for decoding memory addresses for accessing a memory system having a plurality of blocks of memory for storing data at addressable memory locations. Memory addresses are decoded to access the addressable memory locations of a first block of memor... | 07/08/2008 |
| 7353146 | Block processing of input data in graphical programming environments Methods and systems for performing block processing of input data in graphical programming environments are disclosed. The input data that is to be processed is partitioned into a plurality of blocks. Each block of the input data is applied to the data processing un... | 04/01/2008 |
| 7233303 | Method of displaying high-density dot-matrix bit-mapped image on low-density dot-matrix display and system therefor A method of and system for displaying high-density bit-mapped dot-matrix imaging data on a large-scale low-density dot-matrix display is disclosed. Bit-mapped image data from each of multiple and adjacently oriented dot image data groups is allocated to drive one do... | 06/19/2007 |
| 7154501 | Method and apparatus for three-dimensional parallax drawing A three dimensional parallax drawing system for use in three dimensional graphics or virtual reality is disclosed. The parallax drawing system includes a three dimensional address generator which generates the original X-axis, Y-axis and Z-axis addresses of an image... | 12/26/2006 |
| 7151862 | Image processing apparatus and method, storage medium, and program Texture data filtered according to each of different reduction ratio are stored in a texture buffer. A texture mapping apparatus (an lod calculating apparatus) calculates an lod (Level Of Detail) which represents a reduction ratio of each pixel of a polygon. The cal... | 12/19/2006 |
| 7146489 | Methods for intelligent caching in an embedded DRAM-DSP architecture An efficient embedded-DRAM processor architecture and associated methods. In one exemplary embodiment, the architecture includes a DRAM array, a set of register files, set of functional units, and a data assembly unit. The data assembly unit includes a set of row-ad... | 12/05/2006 |
| 7117341 | Storing and selecting multiple data streams in distributed memory devices Prior art storage techniques have certain limitations, including requiring additional external resources to implement and not making use of all of the available storage space. A method and apparatus using a header table and, in some cases, an alternative access inte... | 10/03/2006 |
| 7085804 | Method for processing objects of a standardized communication protocol In a method for processing objects of a standardized communication protocol for image and data exchange between devices via a communication network by means of processing devices, the objects are converted with a conversion routine into a pure text file (plain text)... | 08/01/2006 |
| 7079160 | Method and apparatus using a two-dimensional circular data buffer for scrollable image display A method and apparatus for buffering 2-dimensional graphical image data to be supplied to a scrolling display controller. A 2-dimensional, circularly addressed linear data buffer is used to store a portion of an entire image. The data buffer is larger than the amoun... | 07/18/2006 |
| 7073041 | Virtual memory translation unit for multimedia accelerators A method and system for virtual memory translation of data represented in a multidimensional coordinate system when the physical memory may be located in more than one physical memory location. The translation of one or more virtual addresses into one or more access... | 07/04/2006 |
| 7053900 | Personal computer system and core logic chip applied to same A personal computer system includes a core logic unit, a graphics accelerator, a first tile converter, a local memory, a second tile converter and a system memory. The core logic unit outputs first image data in a linear mode. The graphics accelerator is in communic... | 05/30/2006 |
| 6993781 | Control device, control method, electric apparatus, control method of an electric apparatus, electric apparatus system, control method of an electric apparatus system, and transmission medium Radio waves transmitted from the antenna of a broadcasting station are received by the antenna of a television receiver. The television receiver extracts an EPG from the received radio waves and transmits it to a remote controller via an infrared transmission/recept... | 01/31/2006 |
| 6958757 | Systems and methods for efficiently displaying graphics on a display device regardless of physical orientation The method of one embodiment for the invention is for the CPU to read a subset of consecutive pixels from RAM and cache each such pixel in the WC Cache (and load corresponding blocks into the L2 Cache). These reads and loads continue until the capacity of the L2 Cac... | 10/25/2005 |
| 6954207 | Method and apparatus for processing pixels based on segments There is provided a segment-based pixel processing apparatus and method for effective use of memory. The method includes dividing pixel data within a frame into a plurality of segments in the vertical direction; sequentially pre-processing or post-processing pixel d... | 10/11/2005 |
| 6943804 | System and method for performing BLTs Systems and methods are provided for performing a BLT (BLock Transfer). In accordance with one embodiment, a method uses a texture-mapping subsystem to perform the BLT by configuring the texture-mapping subsystem with coordinate values corresponding to a block of pi... | 09/13/2005 |
| 6922198 | Color signal processing apparatus and method for reproducing colors on MPD A color signal processing apparatus and method calculate without errors a control vector that is a driving signal of a multi-primary display (MPD) corresponding to an input color signal in order to reproduce the input color signal on the MPD using at least four prim... | 07/26/2005 |
| 6876400 | Apparatus and method for protecting a memory sharing signal control lines with other circuitry An apparatus such as a television signal receiver includes first and second circuit boards. The first circuit board includes a memory, and control circuitry for controlling at least one function of the apparatus. The second circuit board is operably coupled to the f... | 04/05/2005 |
| 6870578 | Apparatus and method for sharing signal control lines An apparatus such as a television signal receiver includes first and second circuit boards. The first circuit board includes a first device such as a memory, and control circuitry for controlling at least one function of the apparatus. The second circuit board is op... | 03/22/2005 |
| 6847410 | Picture data memory device with picture data input channels and picture data output channels A picture data memory device which can be used universally comprises a central picture data memory for storing picture data of a plurality of picture data input channels, in which case the stored picture data can additionally be read out via a plurality of picture d... | 01/25/2005 |
| 6784885 | Method and apparatus for three-dimensional parallax drawing A three dimensional parallax drawing system for use in three dimensional graphics or virtual reality is disclosed. The parallax drawing system includes a three dimensional address generator which generates the original X-axis, Y-axis and Z-axis addresses of an image... | 08/31/2004 |
| 6755745 | Display control with fewer amounts of data in game system By using a unique display control technique, game images are provided, in which characters can be displayed in different poses with a limited-capacity memory area. Both image data corresponding to each of a plurality of blocks obtained by dividing a character to be ... | 06/29/2004 |
| 6614443 | Method and system for addressing graphics data for efficient data access A method and apparatus for mapping graphics data of a texture map into virtual two-dimensional (2D) memory arrays implemented in a one-dimensional memory space. The texture map is partitioned into 2u+v two-dimensional arrays having dimensions o... | 09/02/2003 |
| 6563507 | Storage circuit control device and graphic computation device Texture data containing pixel data indicating the color of a plurality of pixels arrayed in matrix fashion are stored in a texture buffer of a DRAM, and the multiple pixel data stored in the texture buffer is simultaneously accessed using a two-dimensiona... | 05/13/2003 |
| 6476818 | Storage circuit control device and graphic computation device Texture data which is two-dimensional image data indicating color data of multiple pixels positioned in a matrix form is stored in a texture buffer of a DRAM, a texture engine circuit combines the bit data making up the U address of a two-dimensional addr... | 11/05/2002 |
| 6125437 | Virtual linear frame buffer addressing method and apparatus A virtual linear frame buffer addressing method and apparatus efficiently convert a linear address supplied by an application programming (API) into an X, Y address used in a rectangular memory addressing arrangement. The virtual linear frame buffer addre... | 09/26/2000 |
| 6088046 | Host DMA through subsystem XY processing A process and implementing computer system in which a graphics subsystem 117 having an XY coordinate addressing system interfaces with a host computer system having a linear addressing configuration. The subsystem includes an internal graphics engine 325,... | 07/11/2000 |
| 6081880 | Processor having a scalable, uni/multi-dimensional, and virtually/physically addressed operand register file A processor is implemented with an operand register file having N operand registers, instructions that reference these operand registers with virtual and physical source and destination addresses of variable up to n addressing dimensions, and at least one... | 06/27/2000 |
| 6072507 | Method and apparatus for mapping a linear address to a tiled address A method and apparatus for mapping a linear address to a tiled address that reduces latency between retrieval of pages of data is accomplished when a video graphics processor receives a linear address from the central processing unit and determines whethe... | 06/06/2000 |
| 6057861 | Mip map/rip map texture linear addressing memory organization and address generator A linear address organization for physically storing mip maps and rip maps in memory is disclosed. The subsampled data arrays of the mip maps and rip maps are sequentially stored in continuous subsequences of a continuous sequence of memory addresses. The... | 05/02/2000 |
| 5781200 | Tile memory mapping for increased throughput in a dual bank access DRAM A method and apparatus for configuring memory within a dual access dynamic random access memory (DRAM) frame buffer so that array conflicts are reduced between neighboring pixels. The present invention DRAM frame buffer contains a number of arrays (e.g., ... | 07/14/1998 |
| 5745739 | Virtual coordinate to linear physical memory address converter for computer graphics system An address generator is disclosed for performing 2-D virtual coordinate to linear physical memory address conversion. The address generator has an edge walking circuit which receives a 2-D virtual coordinate of a first pixel on a first edge of an object d... | 04/28/1998 |
| 5664162 | Graphics accelerator with dual memory controllers A processor having two separate and relatively independent memory controllers to achieve a dual interface architecture. A first memory controller is coupled to the host interface for retrieving data and instructions and a second memory controller is coupl... | 09/02/1997 |
| 5589850 | Apparatus for converting two dimensional pixel image into one-dimensional pixel array An converter apparatus to convert the (X, Y) coordinate of the two-dimensional screen position of a pixel to a linear address. The converter apparatus, which can be used with a variety of video displays of various resolutions including 1280×1024, 1152×9... | 12/31/1996 |
| 5544292 | Display apparatus having a display processor for storing and filtering two dimensional arrays forming a pyramidal array, and method of operating such an apparatus The display apparatus includes a host processor having associated main memory, and a display processor (28', 49 etc.) having an associated texture memory (41') for storing a pyramidal or part-pyramidal array of texture element ("texel") values. Each pyram... | 08/06/1996 |
| 5473348 | Apparatus and method of controlling paging unit of coprocessor built in display control system A comparison result of a comparator in a paging unit determines whether the access target of a coprocessor is a system memory or a VRAM. If the target is a VRAM, predetermined bottom bits of both a TLB tag portion and a linear address to be compared are m... | 12/05/1995 |
| 5388207 | Architecutre for a window-based graphics system A computer graphics system comprises a main CPU, a main system memory and a graphics subsystem for displaying graphical images on a display terminal. A system bus enables the main CPU, main system memory and graphics subsystem to transmit data among one a... | 02/07/1995 |
| 5329617 | Graphics processor nonconfined address calculation system A graphics processing system allows for fuller utilization of memory space by allowing freedom in performing X-Y conversions to linear addressing for graphics display. The system takes advantage of the fact that many display pitch dimensions can be define... | 07/12/1994 |
