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| Number | Title | Issue Date |
| 8098255 | Graphics processing system with enhanced memory controller A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. A memory controller ... | 01/17/2012 |
| 7808507 | Compression tag state interlock Systems and methods for determining a compression tag state prior to memory client arbitration may reduce the latency for memory accesses. A compression tag is associated with each portion of a surface stored in memory and indicates whether or not the data stored in... | 10/05/2010 |
| RE41523 | Graphics engine command FIFO for programming multiple registers using a mapping index with register offsets A host writes graphics commands and data to programmable registers through a command FIFO that is read by a graphics controller or BitBlt engine. Rather than write an address and a data value for each register programmed, the host writes one address, one index, and ... | 08/17/2010 |
| 7724264 | Calculating display mode values Values are calculated which control the manner in which a display streamer directs the movement of display data. The values are stored in the display streamer. ... | 05/25/2010 |
| 7701461 | Method and apparatus for buffering graphics data in a graphics system A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. Techniques for effic... | 04/20/2010 |
| 7570270 | Buffer for driving display with asynchronous display engine Methods and systems for processing pixels within a decoded video stream are disclosed. Processed pixels may be received within the decoded video stream and may be buffered in a buffer at a first rate. The buffered received processed pixels may be transferred out of ... | 08/04/2009 |
| 7426594 | Apparatus, system, and method for arbitrating between memory requests Apparatus, system, and method for arbitrating between memory requests are described. In one embodiment, a processing apparatus includes a memory request generator configured to generate memory requests specifying data for respective presentation elements. The memory... | 09/16/2008 |
| 7425961 | Display panel driver unit To provide an inexpensive display panel driver unit with a built-in memory, which is capable of achieving the same operation as that obtained in using a dual port memory by employing a single port RAM without reduction in an operation speed. A reservation buf... | 09/16/2008 |
| 7423652 | Apparatus and method for digital video decoding The decoding method is disclosed. The steps of the method includes recording each status of a plurality of data blocks of compressed macroblocks indicated by a first pointer to a first pointer storage area and each status of a plurality of data blocks of compressed ... | 09/09/2008 |
| 7400328 | Complex-shaped video overlay using multi-bit row and column index registers A graphics system reduces fetching from memory of color-key pixels when video pixels from a video-overlay window are displayed. A frame buffer is divided into multi-line, multi-pixel blocks that are arranged in block-rows and block-columns. Each block-row has primar... | 07/15/2008 |
| 7366935 | High speed bus with alignment, re-timing and buffer underflow/overflow detection enhancements In a networked system in which high speed busses interconnect sources and destinations of data, systems for and methods of data alignment, data re-timing, and circular buffer underflow/overflow detection, are described. ... | 04/29/2008 |
| 7360035 | Atomic read/write support in a multi-module memory configuration Efficient transfer of data to and from random access memory is described. Multiple request sources and a memory system comprise memory modules having memory banks, each bank containing rows of data. The retrieval comprises transferring all data pursuant to a given r... | 04/15/2008 |
| 7355601 | System and method for transfer of data between processors using a locked set, head and tail pointers A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating process... | 04/08/2008 |
| 7353344 | Storage device The present invention relates to a storage device which receives input of data of arbitrary data length, stores the data, and outputs the stored data in order of input. It provides a storage device capable of unloading data of arbitrary data length from data areas q... | 04/01/2008 |
| 7349027 | Scan converter The scan converter comprises first and second memories 3, 7, a frame memory 5; having a write period and a read period, a video data input circuit 2 for writing data at a first transfer rate into the memory 3, a video data output circuit ... | 03/25/2008 |
| 7339590 | Vertex processing unit supporting vertex texture mapping A graphics processing subsystem includes a vertex processing unit that allows vertex shader programs to arbitrarily access data stored in vertex texture maps. The vertex processing unit includes a vertex texture fetch unit and vertex processing engines. The vertex p... | 03/04/2008 |
| 7340557 | Switching method and system for multiple GPU support A system and method for supporting multiple graphics processing units (GPUs) includes a first communication path coupled to a root complex device and a first connection point of a first GPU. A second communication path is coupled to the root complex device and a fir... | 03/04/2008 |
| 7333116 | Data processor having unified memory architecture using register to optimize memory access In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 | 02/19/2008 |
| 7333114 | System and method for parallel execution of data generation tasks A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating process... | 02/19/2008 |
| 7330927 | Apparatus and methodology for a pointer manager A pointer manager is described. The pointer manager includes write circuitry to enter, into a queue that is implemented with a first memory, a pointer value that a read hub has exhausted the use of. The pointer manager also includes read circuitry to remove, from sa... | 02/12/2008 |
| 7325086 | Method and system for multiple GPU support Supporting multiple graphics processing units (GPUs) comprises a first path coupled to a north bridge device (or a root complex device) and a first GPU, which may include a portion of the first GPU's total communication lanes. A second communication path may be coup... | 01/29/2008 |
| 7321369 | Method and apparatus for synchronizing processing of multiple asynchronous client queues on a graphics controller device An apparatus and method are disclosed for synchronization of command processing from multiple command queues. Various embodiments employ a condition code register that indicates which queues should have processing suspended until a specified event condition occurs. ... | 01/22/2008 |
| 7320004 | System and method for managing database files in a client management tool A system and method for managing database files in a client management tool are provided. A computer system utilizes a standardized format for storing and recalling client management data. To utilize data not stored in the standardized format, the client management ... | 01/15/2008 |
| 7315310 | Clipping device A clipping device for reducing the number of processing cycles, and simplifying the circuit, while increasing the speed of the processing. The clipping device has a clip code generation circuit for generating clip codes corresponding to results of a comparison of ve... | 01/01/2008 |
| 7310100 | Efficient graphics pipeline with a pixel cache and data pre-fetching An efficient graphics pipeline with a pixel cache and data pre-fetching. By combining the use of a pixel cache in the graphics pipeline and the pre-fetching of data into the pixel cache, the graphics pipeline of the present invention is able to take best advantage o... | 12/18/2007 |
| 7301542 | System and method for filtering graphics data on scanout to a monitor A graphics processing system performs filtering of oversampled data during a scanout operation. Sample values are read from an oversampled frame buffer and filtered during scanout; the filtered color values (one per pixel) are provided to a display device without an... | 11/27/2007 |
| RE39898 | Apparatus, systems and methods for controlling graphics and video data in multimedia data processing and display systems A graphics and video controller 105 is provided which includes a dual aperture interface 206 for receiving words of graphics and video pixel data, each word of such data associated with an address directing that word to be processed as either graphics ... | 10/30/2007 |
| 7287107 | Method and apparatus for passive PCI throttling in a remote server management controller The disclosed embodiments relate generally to remote server management technology. More particularly, the embodiments relate to improving the ability of remote server management tools to snoop large amounts of data, including graphical video data, from a communicati... | 10/23/2007 |
| 7284262 | Receiver/decoder and method of processing video data A method of processing video data in a receiver/decoder including at least one port (31) for receiving data and memory means (40) including a data buffer area (45A0, 45A1) for storing incoming data for display, and a... | 10/16/2007 |
| 7280707 | Registration of separations Images may be registered using temporal (time-based) and spatial information. In a film implementation, because film is a sequence of frames, using information from neighboring frames may enable a temporally smoother visual experience. In addition, it may be benefic... | 10/09/2007 |
| 7274371 | Display controller and associated method A data-playing controller includes a register for storing a plurality of control parameters, a first-in-first-out buffer (FIFO) for storing data, and a control circuit capable of accessing a memory dynamically. The register can be electrically connected to a data-pl... | 09/25/2007 |
| 7263280 | Method and/or apparatus for retroactive recording a currently time-shifted program A method for retroactively recording from a circular buffer comprising the steps of (A) determining a starting point in the circular buffer, (B) generating a linear buffer by breaking the circular buffer before the starting point and (C) appending to an ending point... | 08/28/2007 |
| 7259765 | Head/data scheduling in 3D graphics A system for processing graphics data for a stream of graphics primitives, such as triangles. The system has a plurality of memories each for storing an index of the primitive. A controller selects a memory to store the index and assigns a thread id to the index, th... | 08/21/2007 |
| 7259883 | Image processing apparatus, control method of image processing apparatus, and storage medium storing therein control program for image processing apparatus An image processing apparatus which can execute an image process which is desired by a client while minimizing a connection time and an interactive communication between the client and the image processing apparatus is provided. To accomplish the above object, accor... | 08/21/2007 |
| 7250983 | System and method for overlaying images from multiple video sources on a display device The present invention provides a system and method for overlaying video from different video sources on a display device. The sources may include a primary video source that provides first image data in the form of a first video signal, and an overlay video source t... | 07/31/2007 |
| 7248265 | System and method for processing graphics operations with graphics processing unit Disclosed is a system and method for processing graphic operations on a plurality of data structures of an image with a graphics processing unit and memory. The disclosed techniques of the system and method create an accumulation buffer of the data structures for ac... | 07/24/2007 |
| 7243253 | Repeating switching of a cross-connect and a timing source in a network element through the use of a phase adjuster A method and apparatus for enabling repeated switching of a cross-connect and a timing source in a network element through the use of a phase adjuster. In one embodiment, a traffic card includes an aligner to adjust the occupancy of the data in two ingress FIFOs to ... | 07/10/2007 |
| 7224349 | Electronic apparatus The invention efficiently decreases EMI noise occurring with regard to the entirety of an electronic apparatus with a plurality of clocks as references for the operations. The spread spectrum is applied to the clock used by the largest number of ICs, that is, a disp... | 05/29/2007 |
| 7215339 | Method and apparatus for video underflow detection in a raster engine An improved raster engine adapted to render video data from a frame buffer to one of a plurality of disparate displays is disclosed which comprises apparatus for detecting one or more video underflow conditions. The raster engine includes a first in first out (FIFO)... | 05/08/2007 |
| 7194567 | Method and system for ordering requests at a bus interface A bus bridge for coupling between a first bus and a second bus includes: multiple ticket registers; a ticket dispenser counter; and a ticket call counter. The ticket dispenser counter dispenses a ticket value to a request received at the bridge from the first bus fo... | 03/20/2007 |
