"It is my heart-warmed and world-embracing Christmas hope and aspiration that all of us, the high, the low, the rich, the poor, the admired, the despised, the loved, the hated, the civilized, the savage (every man and brother of us all throughout the whole earth), may eventually be gathered together in a heaven of everlasting rest and peace and bliss, except the inventor of the telephone. "
Mark Twain ; Christmas greetings, 1890
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| Number | Title | Issue Date |
| 8094160 | Moving-picture processing apparatus and pre-fetch control method A moving-picture processing apparatus has a pre-fetch memory pre-fetching a portion of a decoded picture stored in an external memory, and a miss/hit determination unit determining a manner in which a miss occurs in response to a read request to the pre-fetch memory... | 01/10/2012 |
| 8035650 | Tiled cache for multiple software programs Caching techniques for storing instructions, constant values, and other types of data for multiple software programs are described. A cache provides storage for multiple programs and is partitioned into multiple tiles. Each tile is assignable to one program. Each pr... | 10/11/2011 |
| 7952588 | Graphics processing unit with extended vertex cache Techniques are described for processing computerized images with a graphics processing unit (GPU) using an extended vertex cache. The techniques include creating an extended vertex cache coupled to a GPU pipeline to reduce an amount of data passing through the GPU p... | 05/31/2011 |
| 7928990 | Graphics processing unit with unified vertex cache and shader register file Techniques are described for processing computerized images with a graphics processing unit (GPU) using a unified vertex cache and shader register file. The techniques include creating a shared shader coupled to the GPU pipeline and a unified vertex cache and shader... | 04/19/2011 |
| 7898551 | Systems and methods for performing a bank swizzle operation to reduce bank collisions Systems and methods for graphics data management are described. One embodiment includes a method for reducing bank collisions within a level 2 (L2) cache comprising the following: reading texture data from external memory configured to store texture data used for te... | 03/01/2011 |
| 7834881 | Operand collector architecture An apparatus and method for simulating a multi-ported memory using lower port count memories as banks. A collector units gather source operands from the banks as needed to process program instructions. The collector units also gather constants that are used as opera... | 11/16/2010 |
| 7808506 | Intelligent caching data structure for immediate mode graphics An intelligent caching data structure and mechanisms for storing visual information via objects and data representing graphics information. The data structure is generally associated with mechanisms that intelligently control how the visual information therein is po... | 10/05/2010 |
| 7796137 | Enhanced tag-based structures, systems and methods for implementing a pool of independent tags in cache memories Disclosed are an apparatus, a system, a method, a graphics processing unit (“GPU”), a computer device, and a computer medium to implement a pool of independent enhanced tags to, among other things, decouple a dependency between tags and cachelines. In one embodi... | 09/14/2010 |
| 7737985 | Pixel cache for 3D graphics circuitry Apparatus are provided including device memory, hardware entities, a sub-image cell value cache, and a cache write operator. At least some of the hardware entities perform actions involving access to and use of the device memory. The hardware entities include 3D gra... | 06/15/2010 |
| 7724263 | System and method for a universal data write unit in a 3-D graphics pipeline including generic cache memories A system and method for a data write unit in a 3-D graphics pipeline including generic cache memories. Specifically, in one embodiment a data write unit includes a first memory, a plurality of cache memories and a data write circuit. The first memory receives a pixe... | 05/25/2010 |
| 7719540 | Render-cache controller for multithreading, multi-core graphics processor A method and apparatus for rendering three-dimensional graphics using a streaming render-cache with a multi-threading, multi-core graphics processor are disclosed. The graphics processor includes a streaming render-cache and render-cache controller to maintain the o... | 05/18/2010 |
| 7626588 | Prescient cache management Prescient cache management methods and systems are disclosed. In one embodiment, a local cache that operates within a raster engine operations stage of a graphics rendering pipeline is managed by following a number of caching decisions related to a number of cached ... | 12/01/2009 |
| 7619633 | Intelligent caching data structure for immediate mode graphics An intelligent caching data structure and mechanisms for storing visual information via objects and data representing graphics information. The data structure is generally associated with mechanisms that intelligently control how the visual information therein is po... | 11/17/2009 |
| 7616210 | Memory apparatus and memory control method A memory apparatus having first and second memories generates an address corresponding to input data, and compares an address corresponding to data stored in the second memory with the generated address. The memory apparatus reads out data corresponding to the gener... | 11/10/2009 |
| 7589738 | Cache memory management system and method A cache memory method and corresponding system for two-dimensional data processing, and in particular, two-dimensional image processing with simultaneous coordinate transformation is disclosed. The method uses a wide and fast primary cache memory (PCM) and a deep se... | 09/15/2009 |
| 7528840 | Optimizing the execution of media processing routines using a list of routine identifiers Methods for analyzing a list of routine identifiers to optimize processing of routines identified in the list. Some embodiments execute a set of routines in multiple passes where each pass comprises each routine in the set processing a single band of its source. The... | 05/05/2009 |
| 7505043 | Cache efficient rasterization of graphics data A cache stores data for use in rasterizing graphics data. The size of the cache is equal to a selected tile size. A processor performs the rasterization of the graphics image by subdividing the graphics image into a plurality of sub-blocks. The sub-blocks are proces... | 03/17/2009 |
| 7477259 | Intelligent caching data structure for immediate mode graphics An intelligent caching data structure and mechanisms for storing visual information via objects and data representing graphics information. The data structure is generally associated with mechanisms that intelligently control how the visual information therein is po... | 01/13/2009 |
| 7439979 | Shader with cache memory A shader having a cache memory for storing program instructions is described. The cache memory beneficially stores both current programming instructions for a fragment program being run and “look-ahead” programming instructions. The cache memory supports a sched... | 10/21/2008 |
| 7427990 | Data replacement method and circuit for motion prediction cache A system for decoding a video bitstream and a method for replacing image data in a motion prediction cache are described. For each of the cache lines, a tag distance between pixels stored in the cache line and uncached pixels that are to be stored in the cache is ca... | 09/23/2008 |
| 7404014 | Method and system for transmitting and determining the effects of display orders from shared application between a host and shadow computer A method and system for compressing bitmap data in a system for sharing an application running on a host computer with a remote computer, wherein the shared application's screen output is simultaneously displayed on both computers. Simultaneous display of screen out... | 07/22/2008 |
| 7372906 | Compression circuitry for generating an encoded bitstream from a plurality of video frames Data is discrete cosine transformed and streamed to a processor where quantized and inverse quantized blocks are generated. A second streaming data connection streams the inverse quantized blocks to an inverse discrete cosine transform block to generate reconstructe... | 05/13/2008 |
| 7369137 | Method for mapping a single decoded content stream to multiple textures in a virtual environment A system includes a computing device to obtain encoded content data corresponding to at least one participant of a virtual reality environment. A memory device stores at least one texture corresponding to the at least one participant. A single decoder decodes the en... | 05/06/2008 |
| 7362904 | Image processing device, image forming apparatus, program, and storing medium Image data of an original image is compressed and encoded by a JPEG2000 algorithm. A position information adding unit adds, to each tile of the code stream, position information indicating a new position in a changed image to form a new code stream. In this manner, ... | 04/22/2008 |
| 7355601 | System and method for transfer of data between processors using a locked set, head and tail pointers A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating process... | 04/08/2008 |
| 7348988 | Texture cache control using an adaptive missing data table in a multiple cache computer graphics environment Provided are methods, systems and graphics processing apparatus, for improving graphics system performance using an adaptive missing table in a multiple cache scheme, such that the table size is dependent on the completeness of the graphics data. ... | 03/25/2008 |
| 7343542 | Methods and apparatuses for variable length encoding Methods and apparatuses for variable length encoding using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor to perform variable length encoding includes: receiving a plurality of parameters, each of the plurality o... | 03/11/2008 |
| 7342589 | System and method for managing graphical data A system and method for managing graphical information are disclosed. The system includes a processing device, first and second memory portions within at least one memory device coupled to the processing device. The first memory portion stores a first plurality of f... | 03/11/2008 |
| 7339590 | Vertex processing unit supporting vertex texture mapping A graphics processing subsystem includes a vertex processing unit that allows vertex shader programs to arbitrarily access data stored in vertex texture maps. The vertex processing unit includes a vertex texture fetch unit and vertex processing engines. The vertex p... | 03/04/2008 |
| 7336710 | Method of motion estimation in mobile device A method of estimating motion in a mobile device reduces access of external memory and power consumption while increasing the usability of internal memory. The method includes recognizing an overlapped block of a reference search area between the current and its nex... | 02/26/2008 |
| 7336274 | Position related information presentation system, position related information presentation method and recording medium recording control program thereof A position related information presentation method, and corresponding system and recording medium storing a corresponding program are provided. The method includes a number of steps. With respect to a display of area information related to a position indicated by da... | 02/26/2008 |
| 7336284 | Two level cache memory architecture A memory architecture for use in a graphics processor including a main memory, a level one (L1) cache and a level two (L2) cache, coupled between the main memory and the L1 cache is disclosed. The L2 cache stores overlapping requests to the main memory before the re... | 02/26/2008 |
| 7333114 | System and method for parallel execution of data generation tasks A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating process... | 02/19/2008 |
| 7330188 | Texture caching arrangement for a computer graphics accelerator A method and apparatus which includes a graphics accelerator, circuitry responsive to pixel texture coordinates to select texels and generate therefrom a texture value for any pixel the color of which is to be modified by a texture, a cache to hold texels for use by... | 02/12/2008 |
| 7328358 | High quality and high performance three-dimensional graphics architecture for portable handheld devices A high quality and performance 3D graphics architecture suitable for portable handheld devices is provided. The 3D graphics architecture incorporates a module to classify polygons by size and other characteristics. In general, small and well-behaved triangles can be... | 02/05/2008 |
| 7322013 | Launch and edit user interface improvements A system and method is described for editing, in its native application, a source file of an object or image in a first application, wherein the source file includes computer-readable code or script associated with the source file and editable in either the first or... | 01/22/2008 |
| 7313764 | Method and apparatus to accelerate scrolling for buffered windows Methods and apparatuses to accelerate scrolling for buffered windows. In one aspect of the invention, a method to scroll a buffered window on a data processing system includes: determining a second region of a second pixel image of a window in a frame buffer, which ... | 12/25/2007 |
| 7313710 | High quality and high performance three-dimensional graphics architecture for portable handheld devices A high quality and performance 3D graphics architecture suitable for portable handheld devices is provided. The 3D graphics architecture incorporates a module to classify polygons by size and other characteristics. In general, small and well-behaved triangles can be... | 12/25/2007 |
| 7310100 | Efficient graphics pipeline with a pixel cache and data pre-fetching An efficient graphics pipeline with a pixel cache and data pre-fetching. By combining the use of a pixel cache in the graphics pipeline and the pre-fetching of data into the pixel cache, the graphics pipeline of the present invention is able to take best advantage o... | 12/18/2007 |
| 7307634 | Systems and methods for efficiently displaying graphics on a display device regardless of physical orientation The method of one embodiment for the invention is for the CPU to read a subset of consecutive pixels from RAM and cache each such pixel in the WC Cache (and load corresponding blocks into the L2 Cache). These reads and loads continue until the capacity of the L2 Cac... | 12/11/2007 |