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| Number | Title | Issue Date |
| 8106917 | Method and system for mosaic mode display of video Methods and systems for mosaic mode display of video are disclosed. Aspects of one method may include generating video data for a plurality of video windows using a single video feeder module comprising a single video scaler and a single video capture module. The vi... | 01/31/2012 |
| 7804505 | Information processing apparatus and associated method of prioritizing content for playback A cache control unit of a video data playback control apparatus sets priority video data in order to efficiently use a storage area of a cache memory. The priority video data includes video data which includes a greater number of portions of video data than that of ... | 09/28/2010 |
| 7796136 | Image signal processing apparatus, memory control method, and program for implementing the method An image signal processing apparatus which is capable of preventing the “simultaneous display of an original image and the immediately preceding image” as well as dropping of frames. A signal processor subjects an image pickup signal corresponding to a subject o... | 09/14/2010 |
| 7683908 | Methods and systems for adaptive image data compression Aspects of the present invention relate to methods and systems for processing image data for use on LCD displays. Some aspects relate to an adaptive image compression techniques for liquid crystal display systems. Some aspects relate to systems and methods wherein v... | 03/23/2010 |
| 7429992 | Method and system for providing accelerated video processing in a communication device Providing accelerated video processing in a communication device may comprise receiving video data from a video source on a chip, determining a first format for at least a portion of the received video data, and determining a second format of at least a remaining po... | 09/30/2008 |
| 7397478 | Various apparatuses and methods for switching between buffers using a video frame buffer flip queue A method, apparatus, and system are described in which a signal is generated to inhibit the execution of flip commands that cause a flip between buffers of a frame buffer. One or more of the flip commands and their associated instruction pointers may be preloaded in... | 07/08/2008 |
| 7386651 | System, method, and apparatus for efficiently storing macroblocks Presented herein is a system for storing macroblocks for such that all vertically, horizontally, and diagonally adjacent macroblock are stored in different banks. When fetching a block from a reference frame that overlaps four macroblocks, each of the overlapped mac... | 06/10/2008 |
| 7379069 | Checkerboard buffer using two-dimensional buffer pages Methods and apparatus for storing and retrieving data using two-dimensional arrays. In one implementation, a checkerboard buffer page system includes: a data source, providing data elements in a first order; a data destination, receiving data elements in a second or... | 05/27/2008 |
| 7366826 | Non-volatile memory and method with multi-stream update tracking Update data to a non-volatile memory may be recorded in at least two interleaving streams such as either into an update block or a scratch pad block depending on a predetermined condition. The scratch pad block is used to buffered update data that are ultimately des... | 04/29/2008 |
| 7362337 | Method and apparatus for adjusting size of image A method for transforming an original image to a new image is provided. The original image includes M rows of original data; the new image includes Q rows of new data. The method first generates a (2i−1)th row and a (2i)th row of intermediate data respectively bas... | 04/22/2008 |
| 7356639 | Configurable width buffered module having a bypass circuit A memory system architecture/interconnect topology includes a configurable width buffered memory module having a configurable width buffer device with at least one bypass circuit. A buffer device, such as a configurable width buffer device, is positioned between or ... | 04/08/2008 |
| 7349027 | Scan converter The scan converter comprises first and second memories 3, 7, a frame memory 5; having a write period and a read period, a video data input circuit 2 for writing data at a first transfer rate into the memory 3, a video data output circuit ... | 03/25/2008 |
| 7321371 | Data conversion device The data conversion device of the present invention includes: a coding section for replacing (i) one or more components constituting the display data of each pixel and other one or more components constituting display data of a pixel existing around that pixel on a ... | 01/22/2008 |
| 7321368 | Electronic system and method for display using a decoder and arbiter to selectively allow access to a shared memory An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the... | 01/22/2008 |
| 7312800 | Color correction of digital video images using a programmable graphics processing unit A system which utilizes the processing capabilities of the graphics processing unit (GPU) in the graphics controller. Each frame of each video stream or track is decoded into a buffer and a color profile indicating parameters of the color space of the video source i... | 12/25/2007 |
| 7313764 | Method and apparatus to accelerate scrolling for buffered windows Methods and apparatuses to accelerate scrolling for buffered windows. In one aspect of the invention, a method to scroll a buffered window on a data processing system includes: determining a second region of a second pixel image of a window in a frame buffer, which ... | 12/25/2007 |
| 7310104 | Graphics display system with anti-flutter filtering and vertical scaling feature A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-... | 12/18/2007 |
| 7304656 | Device for digital display of a video image The present invention relates to a device for digital display of a video image using time-division modulation. This device is intended to display a video image during a video frame comprising a plurality of consecutive subfields distributed within at least two separ... | 12/04/2007 |
| 7304646 | Image data structure for direct memory access A method is provided for transferring data for processing of an image between a first memory and a second memory accessible by a processor. According to such method, data is provided in the first memory for processing of the image, the data being organized into a pl... | 12/04/2007 |
| 7301999 | Quantization method and system for video MPEG applications and computer program product therefor Digital signals are converted between a first and second format by a conversion process including generating coefficients representing the digital signals. The coefficients may be discrete cosine transform coefficient generated during encoding/transcoding of MPEG si... | 11/27/2007 |
| 7302638 | Efficiently displaying and researching information about the interrelationships between documents A system for displaying, on a computer screen, information concerning the interrelationships of documents. A system employing the present invention also allows for the efficient research of documents that cite a document shown on the computer screen. In one embodime... | 11/27/2007 |
| 7287107 | Method and apparatus for passive PCI throttling in a remote server management controller The disclosed embodiments relate generally to remote server management technology. More particularly, the embodiments relate to improving the ability of remote server management tools to snoop large amounts of data, including graphical video data, from a communicati... | 10/23/2007 |
| 7284262 | Receiver/decoder and method of processing video data A method of processing video data in a receiver/decoder including at least one port (31) for receiving data and memory means (40) including a data buffer area (45A0, 45A1) for storing incoming data for display, and a... | 10/16/2007 |
| 7280702 | Methods and apparatus for dynamic transfer of image data A dynamic transfer syntax efficiently transfers data, including large data images, from a server to at least one client. Source data is transformed into a hierarchical representation. The hierarchical representation, consisting of essentially non-redundant data, is ... | 10/09/2007 |
| 7268755 | Architecture for smart LCD panel interface An architecture for a smart liquid crystal display (LCD) panel interface is described. The architecture enables a circuit to transfer only updated display data to the interface. When there are no display data updates to transfer, the circuit is placed in the lowest ... | 09/11/2007 |
| 7262818 | Video system with de-motion-blur processing A video system that performs TV signal decoding, deinterlacing, and de-motion-blurring for progressive scan flat panel display is introduced. The system embeds a frame buffer and a scaler for conducting format and resolution conversions for display panels of differe... | 08/28/2007 |
| 7256797 | Image processing device with synchronized sprite rendering and sprite buffer An image processing device comprises a decoder, a sprite buffer interface, and a sprite buffer as well as a rendering engine, a frame buffer interface, and a frame buffer, which is characterized by synchronizing the write timing for the sprite buffer with the read t... | 08/14/2007 |
| 7256790 | Video and graphics system with MPEG specific data transfer commands A video and graphics system includes a video decoding system for processing compressed video data. The compressed video data includes MPEG-2 video data containing SDTV video data or HDTV video data. The video decoding system includes a video decoder for processing t... | 08/14/2007 |
| 7254776 | Information processing apparatus An information processing apparatus is provided that inputs and outputs images of different resolutions. When a resolution of a line drawing input via an interface is lower than the resolution of the monitor and the resolution of an image input via the interface is ... | 08/07/2007 |
| 7246310 | Efficiently displaying and researching information about the interrelationships between documents A system for displaying, on a computer screen, information concerning the interrelationships of documents. A system employing the present invention also allows for the efficient research of documents that cite a document shown on the computer screen. In one embodime... | 07/17/2007 |
| 7233336 | Systems and methods for capturing screen displays from a host computing system for display at a remote terminal The present invention provides systems and methods for monitoring a host computing system from a maintenance computing system located at a remote location. The system of the present invention includes a frame grabber that is connected the digital output of a video c... | 06/19/2007 |
| 7227554 | Method and system for providing accelerated video processing in a communication device Providing accelerated video processing in a communication device may comprise receiving video data from a video source on a chip, determining a first format for at least a portion of the received video data, and determining a second format of at least a remaining po... | 06/05/2007 |
| 7227584 | Video signal processing system A video signal processing system for processing a video data VIN and graphic data DμP includes a filter unit, which receives the video data VIN. The filter unit filters the video data VIN to convert the video data VI... | 06/05/2007 |
| 7218789 | Method for lossless encoding of image data by approximating linear transforms and preserving selected properties for image processing A method for generating a first plurality of output data values and the matrix factors used to generate an approximation to an image processing transform is disclosed. The first plurality of output data values are generated by transforming a plurality of input data ... | 05/15/2007 |
| 7206896 | Integrated circuit buffer device An integrated circuit buffer device comprises a first receiver circuit to receive control information and address information from a controller device. A first interface includes a first interface portion to provide a first address to a first memory device. A second... | 04/17/2007 |
| 7206897 | Memory module having an integrated circuit buffer device A memory module includes an integrated circuit buffer device that receives control information via a connector interface. A first plurality of signal lines carries a first address from the integrated circuit buffer device to a first memory device. A second plurality... | 04/17/2007 |
| 7203518 | Method and apparatus for simplified data dispensation to and from digital systems A wireless data retrieval device and method for implementing the same. In accordance with one embodiment of the invention, the wireless data retrieval device includes a first-in-first-out (FIFO) memory queue in the form of a linked list that stores standardized corr... | 04/10/2007 |
| 7203366 | Video retrieval method and apparatus A method of characterizing a video includes the steps of extracting frame images from an input video, calculating a time length between each of the frame images and a next one of the frame images, assigning index information determined by the calculated time length ... | 04/10/2007 |
| 7200710 | Buffer device and method of operation in a buffer device An integrated circuit buffer device comprising a receiver circuit to receive control information and address information. A first interface portion provides at least a first control signal that specifies a write operation to a first memory device. The first control ... | 04/03/2007 |
| 7196708 | Parallel vector processing A video platform architecture provides video processing using parallel vector processing. The video platform architecture includes a plurality of video processing modules, each module including a plurality of processing elements (PEs). Each PE provides parallel vect... | 03/27/2007 |
