Did You Know...
...that Thomas Edison's patent application on his phonograph was approved by the Patent Office in just seven weeks? In contrast, it took Gordon Gould, the inventor of the laser, 30 years to obtain his patent -- finally awarded in 1988!
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| Number | Title | Issue Date |
| 6639603 | Hardware portrait mode support A display subsystem supports both normal mode and portrait mode displays. In normal mode, the scan starts at the upper left comer of the display. In portrait mode, the scan starts at the lower left comer of the display. The display subsystem includes a du... | 10/28/2003 |
| 6636224 | Method, system, and computer program product for overlapping graphics data collection and transmission using a single processor A method, system, and computer program product sends scene data to a geometry engine, wherein a processor generates scene data for a frame in accordance with an application program, and writes the scene data to a first memory location, known hereinafter a... | 10/21/2003 |
| 6633298 | Creating column coherency for burst building in a memory access command stream A buffer facilitates reordering of memory access commands in a memory access command stream so as to create column coherencies that may be exploited with burst-mode memory cycles. A multi-column data storage buffer is provided. Storage control circuitry s... | 10/14/2003 |
| 6628291 | Method and apparatus for display refresh using multiple frame buffers in a data processing system A frame buffer system includes a first frame buffer containing a first set of pixels, and a second frame buffer containing a second set of pixels. A first register is connected to an output of the first frame buffer, wherein the first register a number of... | 09/30/2003 |
| 6622213 | Two-way cache system and method for interfacing a memory unit with a peripheral device using first and second cache data regions A two-way cache system for interfacing with a peripheral device and a method of operating a two-way cache system for carrying out data transmission between a peripheral device and a memory unit. The cache system has a two-way first-in first-out buffer reg... | 09/16/2003 |
| 6621496 | Dual mode DDR SDRAM/SGRAM A dual-mode dual-data rate (DDR) synchronous dynamic random access memory (SDRAM)/synchronous graphic random access memory (SGRAM). An exemplary DDR SDRAM/SGRAM comprises a single memory device, which itself comprises a memory array and a logic circuitry.... | 09/16/2003 |
| 6614442 | Macroblock tiling format for motion compensation A macroblock tiling format method and system for implementing the method during an MPEG decoding process is disclosed. The macroblock tiling format groups picture data samples into tiles, each tile including a combination of luminance and/or chrominance d... | 09/02/2003 |
| 6614444 | Apparatus and method for fragment operations in a 3D-graphics pipeline Apparatus and methods for rendering 3D graphics images. The apparatus include a port for receiving commands from a graphics application, an output for sending a rendered image to a display and a fragment-operations pipeline, coupled to the port and to the... | 09/02/2003 |
| 6611272 | Method and apparatus for rasterizing in a hierarchical tile order A method and apparatus for efficiently rasterizing graphics is provided. The method is intended to be used in combination with a frame buffer that provides fast tile-based addressing. Within this environment, frame buffer memory locations are organized in... | 08/26/2003 |
| 6611274 | System method, and computer program product for compositing true colors and intensity-maped colors into a frame buffer The color of a pixel is represented in a pixel storage word, wherein color coordinate data and intensity data are coded separately in two fields of the pixel storage word, the color field and the intensity field. This permits a range of colors to be repre... | 08/26/2003 |
| 6597363 | Graphics processor with deferred shading Graphics processors and methods are described that encompass numerous substructures including specialized subsystems, subprocessors, devices, architectures, and corresponding procedures. Embodiments of the invention may include one or more of deferred sha... | 07/22/2003 |
| 6587158 | Method and apparatus for reducing on-chip memory in vertical video processing A digital image processor includes an input buffer for storing raster-scanned data. A slice-buffer memory is coupled to the input buffer to store a portion of a vertical slice of said raster-scanned data. The vertical slice is processed by a vertical slic... | 07/01/2003 |
| 6577303 | Apparatus and method for detecting DVI connectors of a digital video display device An apparatus and a method for determining a type of DVI (Digital Visual Interface) connector connected to a digital video display device, wherein the apparatus utilizes a first resistor connected between a voltage source and a node; a second resistor conn... | 06/10/2003 |
| 6567094 | System for controlling read and write streams in a circular FIFO buffer A distributed digital imaging processing system having a number of processing units and circular FIFO buffers connected together using data transforming streams. Processing units read data from buffers using a transforming read streams. These read streams... | 05/20/2003 |
| 6567099 | Method and system for dynamically allocating a frame buffer for efficient anti-aliasing An anti-aliasing system provides anti-aliasing at the edges of objects in a displayed or printed image without video artifacts or the need for an expensive anti-aliasing buffer. As geometric data is rasterized, the rasterizer identifies pixels on the edge... | 05/20/2003 |
| 6538662 | Efficient pixel packing In storing data for display, traditionally twenty-four bit video pixels have required extra video memory to store the video pixels on double word boundaries or extensive hardware to fully utilize video memory. Eight twenty-four bit video pixels are stored... | 03/25/2003 |
| 6535218 | Frame buffer memory for graphic processing A frame buffer memory is disclosed which provides accelerated rendering of two-dimensional and three-dimensional images in a computer graphics system. One embodiment of the disclosed memory comprises a memory array, a pixel buffer, a plurality of pixel ar... | 03/18/2003 |
| 6522335 | Supplying data to a double buffering process Data is supplied to a double buffering process. New data is supplied to a background buffer for a displayed item. A condition is identified to the effect that the item in a foreground buffer is invalid. On the previous cycle, a similar process may have be... | 02/18/2003 |
| 6518973 | Method, system, and computer program product for efficient buffer level management of memory-buffered graphics data A method, system, and computer program product is provided for managing the efficient transfer of graphics data to a graphics rendering system. A graphics application program writes graphics data to graphics buffers that are allocated in virtual memory. E... | 02/11/2003 |
| 6515672 | Managing prefetching from a data buffer A method and apparatus for preventing over-prefetching from a buffer receives an address of a last data set item in a data buffer, and reads data from the data buffer into a read streamer buffer starting at a data buffer start address until the address of... | 02/04/2003 |
| 6509897 | Method and system for providing implicit edge antialiasing A method and system for providing antialiasing of a graphical image on a display from data describing at least one object is disclosed. The display includes a plurality of pixels. The method and system include providing a plurality of fragments for the at... | 01/21/2003 |
| 6510470 | Mechanism allowing asynchronous access to graphics adapter frame buffer physical memory linear aperture in a multi-tasking environment A module is interposed between a multitasking operating system and the device driver for a graphics adapter including a frame buffer with a linear aperture for continuous, asynchronous data transfers. The interposed module may selectively intercept all gr... | 01/21/2003 |
| 6504547 | Standardization of graphics system logical frame buffer A method for implementing a bitmapped graphics system involves creating a logical frame buffer for a program. The method attaches a standardization operation to the logical frame buffer, so that the standardization operation is automatically executed upon... | 01/07/2003 |
| 6504549 | Apparatus to arbitrate among clients requesting memory access in a video system and method thereof A method and apparatus dealing with optimizing the arbitration between clients requesting data. In particular, a set of rules determining which client request will provide an optimized subsequent memory access is implemented. The highest rule recognizes a... | 01/07/2003 |
| 6504550 | System for graphics processing employing semiconductor device A graphics processing system which employs one or more frame buffer memory devices is disclosed which system provides accelerated rendering of two-dimensional and three-dimensional images. One embodiment of the disclosed system comprises a rendering contr... | 01/07/2003 |
| 6496160 | Stroke to raster converter system An apparatus for converting analog stroke display signals representing electron beam generated stroke traces into raster display information for producing a raster-scan image display. The apparatus includes a sampling circuit for sampling the analog strok... | 12/17/2002 |
| 6489964 | Memory arrangement In a memory arrangement including a frame buffer unit (FB) having memory equipment (SDRAM) clocked by a memory clock (fm), and a scaler unit (S), the scaler unit (S) has at least one line memory (inplinmem, outplinmem) for converting a continuous input da... | 12/03/2002 |
| 6483515 | Method and apparatus for displaying data patterns in information systems A method of updating a remote display device associated with a remote system to fill at least a portion of a display area on the display device with a tiled pattern including repetitions of a tile image data stored at a host system interconnected to the r... | 11/19/2002 |
| 6466218 | Graphics system interface An interface for a graphics system includes simple yet powerful constructs that are easy for an application programmer to use and learn. Features include a unique vertex representation allowing the graphics pipeline to retain vertex state information and ... | 10/15/2002 |
| 6466216 | Computer system with optimized display control A computer system having an optimized display controller is disclosed. The computer system has a central processing unit connected to a system bus. Within the computer system, both a system memory and a video memory are connected in parallel to the system... | 10/15/2002 |
| 6462746 | On screen display memory structure in a digital video display unit and method therefor A memory structure and method for implementing an on screen display (OSD) is disclosed. The present invention separates a command area, which stores small but frequently updated data causing fatal errors due to erroneous read, from a bitmap area, which st... | 10/08/2002 |
| 6437809 | Secondary user interface An alternate display content controller provides a technique for controlling a video display separately from and in addition to the content displayed on the operating system monitor. Where the display is a computer monitor, the alternate display content c... | 08/20/2002 |
| 6424350 | Method of controlling a liquid crystal display A method of controlling a liquid crystal display, the method being of the type requiring refreshment of the displayed information in successive stages, a refresh stage having the following steps: executing at least one request to access a shared memory, s... | 07/23/2002 |
| 6417859 | Method and apparatus for displaying video data This invention provides a method to control the buffering of encoded video data organized as frames or fields. This method involves determining the picture number of each incoming decoded frame, determining the expected presentation number at any time and... | 07/09/2002 |
| 6411302 | Method and apparatus for addressing multiple frame buffers High resolution image data is stored in multiple frame buffers to enable the image data to be coupled to multiple lower resolution video streams. Despite physical address discontinuities at frame buffer crossover boundaries, addressing of the multiple fra... | 06/25/2002 |
| 6400361 | Graphics processor architecture employing variable refresh rates The display system includes a display controller which renders text and graphics and writes it to the RAM. The display controller then reads the rendered information from the RAM and activates a display based upon that information. Generally the display c... | 06/04/2002 |
| 6384831 | Graphic processor and data processing system In a graphic processor, a rendering control circuit carries out weighted averaging on pieces of pixel data of source image information arranged to form a pixel-data matrix corresponding to a pixel matrix with columns of the pixel-data matrix being oriente... | 05/07/2002 |
| 6366288 | Image display control apparatus for displaying images corresponding to action of an object In an image display device, a ROM contains a plurality of image data indicative of the actions of an animal character. A RAM includes a plurality of action level registers each stores for each of which image data the state of inputs given to select and di... | 04/02/2002 |
| 6363451 | Data bus line control circuit A data bus line control circuit prevents a problem of a data access operation on a global data bus (GDB) line although two blocks are simultaneously selected. The data bus line control circuit includes: a global data bus line which is arranged between mem... | 03/26/2002 |
| 6337690 | Technique for reducing the frequency of frame buffer clearing A clear color and count are stored in a frame buffer controller and in a video controller. The image buffer is cleared by writing the clear color into a color bit field and the count into a count bit field of each pixel. For each frame drawn, the count bi... | 01/08/2002 |
