Bizarre Patents
Cloaking System Using Optoelectronically Controlled Camouflage
A Cloaking System designed to operate in the visible light spectrum, utilizes optoelectronics and/or photonic components to conceal an object within it.
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| Number | Title | Issue Date |
| 8102400 | Method and apparatus for providing enhanced resolution display for display telephones and PDAs In a mobile device with a mobile device video driver that can be interdicted, such as a display telephone or PDA, a method and system for display on a remote video display device is provided involving forming an enhanced display image in an enhanced video frame buff... | 01/24/2012 |
| 8063910 | Double-buffering of video data Data is written to one of two frame buffers in write access cycles having write and non-write sub-periods. Data is read out to a display device from the other of the two frame buffers in read access cycles having read and non-read sub-periods. The writing of data an... | 11/22/2011 |
| 8004535 | Apparatus and method for selectively double buffering portions of displayable content A method of generating displayable content is provided. The method includes obtaining a display package having a plurality of display elements defining a plurality of display frames. The method further includes rendering at least one selected group of the plurality ... | 08/23/2011 |
| 7812849 | Event memory assisted synchronization in multi-GPU graphics subsystem A method and system are disclosed for synchronizing graphics processing events in a multi-GPU computer system. A master GPU renders a first image into a first portion of a master buffer associated with a display interface, and then writes a first predetermined value... | 10/12/2010 |
| 7683906 | Frame buffer control for smooth video display Video frame buffers are controlled using a sequence of new-frame-indicators (e.g., FLIP) and no-new-frame-indicators (e.g., NOFLIP) in a frame indicator queue that is accessed with each display refresh. Video samples are loaded into a chain of video frame buffers th... | 03/23/2010 |
| 7554551 | Decoupling a color buffer from main memory A display color buffer in a unified memory architecture is decoupled from main memory by partitioning the address space for the color buffer into a frame-preparation memory accessed by a graphics subsystem at a frame rate to prepare color data and a refresh memory t... | 06/30/2009 |
| 7489316 | Method for frame rate conversion A method for converting a frame rate of a video signal comprising a data enable signal by means of a first buffer and a second buffer is disclosed. The method comprises: alternatively accessing the first buffer and the second buffer according to a first frame rate; ... | 02/10/2009 |
| 7439983 | Method and apparatus for de-indexing geometry A pixel shader is operated to perform a first texture lookup in an index buffer to obtain a vertex index value for a geometric primitive to be displayed. The pixel shader is also operated to perform a second texture lookup in a vertex buffer to obtain vertex data, w... | 10/21/2008 |
| 7439981 | Methods and systems for displaying animated graphics on a computing device Disclosed are methods and systems for interfaces between video applications and display screens that allow applications to intelligently use display resources of their host device without tying themselves too closely to operational particulars of that host. A graphi... | 10/21/2008 |
| 7425962 | Systems and methods for generating a composite video signal from a plurality of independent video signals Illustrated and described embodiments are broadly directed to novel systems and methods for generating a composite video signal from a plurality of independent video signals. In accordance with one embodiment, a method is provided for swapping from a secondary frame... | 09/16/2008 |
| 7423644 | Method and apparatus for dual pass adaptive tessellation A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shad... | 09/09/2008 |
| 7372461 | Image processing apparatus and method of same An image processing apparatus able to decrease the number of minute unit graphics, able to achieve an improvement of performance of graphics drawing processing, and able to efficiently generate images, provided with a triangle generator for receiving vertex data fro... | 05/13/2008 |
| 7369139 | Background rendering of images An apparatus includes a rendering engine to render a foreground of an image. The apparatus also includes a logic, separate from the rendering engine, to merge at least one background color with the foreground of the image. ... | 05/06/2008 |
| 7365743 | Assignments for parallel rasterization Methods and apparatus, including computer program products, to rasterize an image by generating assignments and allocating the assignments among multiple processor threads such that no two processor threads are rasterizing concurrently into overlapping regions of a ... | 04/29/2008 |
| 7336264 | Method and system for editing or modifying 3D animations in a non-linear editing environment A non-linear editing (NLE) system for editing and/or modifying 3D animation information comprises elements represented by clip objects which can be positioned and/or manipulated relative to a time line. The elements can comprise conventional 1D (audio) or 2D (video)... | 02/26/2008 |
| 7327371 | Graphic controller, microcomputer and navigation system Image data storage areas of a plurality of pages are allocated for each of a plurality of display planes capable of superimposed display, and display output processing is performed while switching between the image data storage areas is being performed for each disp... | 02/05/2008 |
| 7310332 | Network switch memory interface configuration A network switch for network communications includes a first data port interface, wherein the first data port interface supports a plurality of data ports for transmitting and receiving data at a first data rate. The network switch also includes a second data port i... | 12/18/2007 |
| 7307641 | Method and apparatus for transforming display data using multiple frame buffers in a display device Methods and systems for transforming data in a system are provided. In one implementation, the method includes providing a first frame buffer, and providing a second frame buffer that is separate from the first frame buffer. The first frame buffer is configured to s... | 12/11/2007 |
| 7295249 | Digital television display control apparatus and method Apparatus for controlling a digital television display, the apparatus comprising a main processor 4, a main memory 5 coupled to said main processor 4 via address and data busses, the main memory 5 being arranged to store at least temporar... | 11/13/2007 |
| 7289131 | Method of rendering a graphics image A method of rendering a graphics image in which rendering is only carried out in a region to be changed is disclosed. In a preferred form the image includes a plurality of objects and the method comprises the steps of: determining if each object has changed so that ... | 10/30/2007 |
| 7277132 | Method for motion vector de-interlacing A method for motion vector de-interlacing decodes macro blocks in a picture, calculates motion vectors of the each MB, produces de-interlacing flag according to the threshold, realizes a Temporal Extension action and performs a Devour action. The Temporal Extension ... | 10/02/2007 |
| 7271808 | Image display control method and image display control apparatus When a contention is detected between a memory write address and a display read address in a memory circuit which stores display data, a host retry pulse generating circuit generates a display read signal and a display line data transfer signal based on a memory wri... | 09/18/2007 |
| 7268755 | Architecture for smart LCD panel interface An architecture for a smart liquid crystal display (LCD) panel interface is described. The architecture enables a circuit to transfer only updated display data to the interface. When there are no display data updates to transfer, the circuit is placed in the lowest ... | 09/11/2007 |
| 7266255 | Distributed multi-sample convolution A multi-chip system is disclosed for distributing the convolution process. Rather than having multiple convolution chips working in parallel with each chip working on a different portion of the screen, a new design utilizes chips working in series. Each chip is resp... | 09/04/2007 |
| 7263128 | Triple-buffering method for overlapped motion compensation in a video decoder A method of improving performance within video decoders subject to the execution of overlapped motion compensation. The method utilizes a triple-buffering approach to achieve rapid data transfers and to eliminate transfer and decoding delays. Each of the three buffe... | 08/28/2007 |
| 7262776 | Incremental updating of animated displays using copy-on-write semantics Tile buffers in a graphics processing system are managed using “copy-on-write” semantics, in which tile data stored in a memory location is not transferred to another location until the tile data for one of the buffers is modified, thereby providing copy on flip... | 08/28/2007 |
| 7254780 | System, device and method for controlling display presentation order The invention provides a display control system in which the troublesomeness and time required for the presentation and the number of misses upon presentation can be reduced, and a presenter can flexibly respond to the status change of the scheduling of display orde... | 08/07/2007 |
| 7248265 | System and method for processing graphics operations with graphics processing unit Disclosed is a system and method for processing graphic operations on a plurality of data structures of an image with a graphics processing unit and memory. The disclosed techniques of the system and method create an accumulation buffer of the data structures for ac... | 07/24/2007 |
| 7245945 | Portable computing device adapted to update display information while in a low power mode Briefly, in accordance with one embodiment of the invention, a portable computing device that has a processor, a direct memory access (DMA) engine, and a display controller may transfer data with the DMA engine to the display. The DMA engine may transfer the data wh... | 07/17/2007 |
| 7242437 | Compressed timing indicators for media samples A first frame of data is encoded and a first timestamp associated with the first frame of data is generated. The first timestamp includes complete timing information. The first frame of data and the associated first timestamp is transmitted to a destination. A secon... | 07/10/2007 |
| 7239324 | Methods and systems for merging graphics for display on a computing device Disclosed are methods and systems that allow video applications to merge their outputs for display and to transform the outputs of other applications before display. A graphics arbiter tells applications the estimated time when the next frame will be displayed on a ... | 07/03/2007 |
| 7234028 | Power/performance optimized cache using memory write prevention through write snarfing A multiprocessor system may include multiple processors and multiple caches associated with the processors. The system may employ a memory snarfing technique to reduce writes to the system (or main) memory. Cache-ownership capable agents, e.g., agents with write-bac... | 06/19/2007 |
| 7231632 | System for reducing the number of programs necessary to render an image A system for reducing memory and computational requirements of graphics operations. The system provides techniques for combining otherwise individual operations to apply filters to images. A combined filter emerging from the combination spares the processor time and... | 06/12/2007 |
| 7227551 | Manipulating text and graphic appearance A method, device and computer system for creating a smooth, continuous height (scalar or vector) field are described. The described techniques permit arbitrary closed regions to be smoothly shaded without producing unnatural smoothness at the region's edges or bound... | 06/05/2007 |
| 7224368 | Rendering tear free video Systems and methods to render tear free video in a multitasking operating environment are described. In one aspect, a video playback window portion of a desktop display is divided into non-overlapping first and second partitions. As video data is scanned into displa... | 05/29/2007 |
| 7219170 | Burst transfer register arrangement Machine-readable media, methods, and apparatus are described to burst write a command and its arguments to control registers of a device and to burst read status and outputs of the command from control registers of the device. During the burst write, the arguments m... | 05/15/2007 |
| 7205993 | Checkerboard buffer using two-dimensional buffer pages and using memory bank alternation Methods and apparatus for storing and retrieving data. In one implementation, a system includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least four memories, each having memory pages, data stored to at... | 04/17/2007 |
| 7176850 | Overlay process of images The present invention provides a technology that enables projection images to be overlaid with embellishment effects without depending on the capabilities of the image supply apparatus. A projection display apparatus that projects images onto a screen responsive to ... | 02/13/2007 |
| 7176848 | Method of synchronizing images on multiple display devices with different refresh rates A method for displaying images on multiple monitors with different refresh rates is disclosed. To prevent screen tearing, the surface containing image data is not released when the access by the master monitor is completed until the slave monitor or monitors finish ... | 02/13/2007 |
| 7170471 | Plasma display apparatus and method of driving a plasma display panel An interlace-type PDP is driven by an improved driving method so as to achieve a greater operating margin, higher resolution, and higher brightness. The interlace-type PDP is driven using odd and even frames in such a manner that the cells are grouped into cell grou... | 01/30/2007 |
