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| Number | Title | Issue Date |
| 8139073 | Early compression tag lookup for memory accesses Systems and methods for determining a compression tag state prior to memory client arbitration may reduce the latency for memory accesses. A compression tag is associated with each portion of a surface stored in memory and indicates whether or not the data stored in... | 03/20/2012 |
| 8106915 | Display control circuit and display device A display control circuit capable of performing arbitration with the use of a simple configuration. The display control circuit exchanges, with a plurality of masters, attribute information defining conditions for displaying video on a display, and includes a memory... | 01/31/2012 |
| RE41413 | Computer system controller having internal memory and external memory control The present invention relates generally to an optimized memory architecture for computer systems and, more particularly, to integrated circuits that implement a memory subsystem that is comprised of internal memory and control for external memory. The invention incl... | 07/06/2010 |
| 7538772 | Graphics processing system with enhanced memory controller A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. A memory controller ... | 05/26/2009 |
| 7417637 | Fairly arbitrating between clients An apparatus and method for fairly arbitrating between clients with varying workloads. The clients are configured in a pipeline for processing graphics data. An arbitration unit selects requests from each of the clients to access a shared resource. Each client provi... | 08/26/2008 |
| 7400327 | Apparatus, system, and method for a partitioned memory A memory system having a number of partitions each operative to independently service memory requests from a plurality of memory clients while maintaining the appearance to the memory client of a single partition memory subsystem. The memory request specifies a loca... | 07/15/2008 |
| 7369131 | Multi-display system and method thereof A multi-display system and a method thereof which solves an overloading problem on a memory bus. The multi-display system includes displays which independently display separate images, a main memory which stores input image signals, image signal process units which ... | 05/06/2008 |
| 7369133 | Apparatus, system, and method for a partitioned memory for a graphics system A memory system having a number of partitions each operative to independently service memory requests from a plurality of memory clients while maintaining the appearance to the memory client of a single partition memory subsystem. The memory request specifies a loca... | 05/06/2008 |
| 7360020 | Method for improving cache-miss performance A cache memory with improved cache-miss performance is implemented by providing cache-miss data from system memory directly to its requester. One embodiment of the invention operates as a texture cache in a graphics system. The graphics system comprises a system mem... | 04/15/2008 |
| 7360068 | Reconfigurable signal processing IC with an embedded flash memory device A dynamically reconfigurable processing unit includes a microprocessor, and an embedded Flash memory for non-volatile storage of code, data and bit-streams. The embedded Flash includes a field programmable gate array (FPGA) port. The reconfigurable processing unit f... | 04/15/2008 |
| 7340562 | Cache for instruction set architecture A distributed data cache includes a number of cache memory units or register files each having a number of cache lines. Data buses are connected with the cache memory units. Each data bus is connected with a different cache line from each cache memory unit. A number... | 03/04/2008 |
| 7340557 | Switching method and system for multiple GPU support A system and method for supporting multiple graphics processing units (GPUs) includes a first communication path coupled to a root complex device and a first connection point of a first GPU. A second communication path is coupled to the root complex device and a fir... | 03/04/2008 |
| 7334063 | Method and device for register access according to identifier register A method for accessing digital data information is used for reducing accessing time when a processor accesses digital data from a register. The method comprises the steps of accessing data from a register with a processor, continuously accessing data from the regist... | 02/19/2008 |
| 7325086 | Method and system for multiple GPU support Supporting multiple graphics processing units (GPUs) comprises a first path coupled to a north bridge device (or a root complex device) and a first GPU, which may include a portion of the first GPU's total communication lanes. A second communication path may be coup... | 01/29/2008 |
| 7321368 | Electronic system and method for display using a decoder and arbiter to selectively allow access to a shared memory An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the... | 01/22/2008 |
| 7313764 | Method and apparatus to accelerate scrolling for buffered windows Methods and apparatuses to accelerate scrolling for buffered windows. In one aspect of the invention, a method to scroll a buffered window on a data processing system includes: determining a second region of a second pixel image of a window in a frame buffer, which ... | 12/25/2007 |
| 7302585 | System for providing a trustworthy user interface The preferred embodiment of the invention comprises a computer system which employs a trusted display processor (260), which has a trusted processor (300) and trusted memory (305, 315, 335, 345) physically and functionally distinct from the proc... | 11/27/2007 |
| 7284262 | Receiver/decoder and method of processing video data A method of processing video data in a receiver/decoder including at least one port (31) for receiving data and memory means (40) including a data buffer area (45A0, 45A1) for storing incoming data for display, and a... | 10/16/2007 |
| 7271808 | Image display control method and image display control apparatus When a contention is detected between a memory write address and a display read address in a memory circuit which stores display data, a host retry pulse generating circuit generates a display read signal and a display line data transfer signal based on a memory wri... | 09/18/2007 |
| 7265758 | Communication protocol for synchronizing animation A communications protocol is described that governs asynchronous exchange of data between a high level animation system and a low level animation system. The high level animation system has a variable, medium-frequency frame rate and is optimized for interactivity. ... | 09/04/2007 |
| 7257673 | Ternary CAM with software programmable cache policies A circuit comprising a plurality of first line buffers, an arbiter and a cache. The plurality of first line buffers may be configured to communicate on a plurality of first busses. The arbiter may be configured to perform an arbitration among the first line buffers.... | 08/14/2007 |
| 7253818 | System for testing multiple devices on a single system and method thereof A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directe... | 08/07/2007 |
| 7239326 | Method and system for providing edge antialiasing A system and method for generating a graphical image on a display is disclosed. The graphical image is generated from data describing at least one object. The display includes a plurality of positions. Each of the plurality of positions has an area. The system and m... | 07/03/2007 |
| 7239324 | Methods and systems for merging graphics for display on a computing device Disclosed are methods and systems that allow video applications to merge their outputs for display and to transform the outputs of other applications before display. A graphics arbiter tells applications the estimated time when the next frame will be displayed on a ... | 07/03/2007 |
| 7239323 | Color display driving apparatus in a portable mobile telephone with color display unit A color display driving apparatus that simultaneously on-screen displays an RGB format color image and a YUV format color image on the same color display unit. A first memory stores YUV data, and a YUV-RGB converter converts YUV data read from the first memory to RG... | 07/03/2007 |
| 7239322 | Multi-thread graphic processing system The present invention includes a multi-thread graphics processing system and method thereof including a reservation station having a plurality of command threads stored therein. The system and method further includes an arbiter operably coupled to the reservation st... | 07/03/2007 |
| 7233323 | Device and method for varying the row scanning time to compensate the signal attenuation depending on the distance between pixel rows and column driver A display device having a control circuit for changing a time period of applying a signal voltage to each of the signal lines and a scanning voltage to each of the scanning lines within one vertical scanning period (T). The control circuit controls each of horizonta... | 06/19/2007 |
| 7233335 | System and method for reserving and managing memory spaces in a memory resource System and method for reserving a memory space for multithreaded processing is described. Memory space within a memory resource is allocated responsive to thread type. Examples of thread types for graphics processing include primitive, vertex and pixel types. Memory... | 06/19/2007 |
| 7212211 | Data processing system and method, computer program, and recording medium The present invention provides data processing technology for making two or more processing units cooperate with one another such that output data from respective groups of processing units (GSM) are merged by a respective sub-MG (merger), data from the sub-MGs are ... | 05/01/2007 |
| 7213109 | System and method for providing speculative ownership of cached data based on history tracking A system and method for managing memory data is provided. Data stored within a main memory may be requested by multiple requesters that may include one or more cache memories. When the data is provided by the main memory to a requester, it will be provided in a stat... | 05/01/2007 |
| 7209186 | Image processing apparatus and image processing method for high speed real-time processing The present invention provides an image processing apparatus and an image processing method. The image processing apparatus includes: a first to a fourth writing FIFO unit and a first to a fourth reading FIFO unit (hereinafter referred to as “FIFO units”) for te... | 04/24/2007 |
| 7209992 | Graphics display system with unified memory architecture A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that ... | 04/24/2007 |
| 7202871 | Texture engine memory access synchronizer An arbitration mechanism for balancing memory requests issued by parallel texture pipelines in a multiple pipeline texture engine. The mechanism ensures that, as polygon textures are processed by a texture engine, all of the memory requests associated with a portion... | 04/10/2007 |
| 7202882 | Liquid crystal display device A liquid crystal display device employing an overshooting driving method is provided which is capable of reducing memory capacity of a frame memory used to delay input data. The above liquid crystal display device for displaying an image using a liquid crystal panel... | 04/10/2007 |
| 7191292 | Logging of level-two cache transactions into banks of the level-two cache for system rollback A plurality of processors on a chip is operated in lockstep. A crossbar switch on the chip couples and decouples the plurality of processors to a plurality of banks in a level-two (L2) cache. As data is stored in a first bank of the L2 cache, the old d... | 03/13/2007 |
| 7191321 | Microengine for parallel processor architecture A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control ... | 03/13/2007 |
| 7180520 | Queue partitioning mechanism According to one embodiment a chipset is disclosed. The chipset includes a graphics accelerator, a memory controller and a queue mechanism. The queue mechanism includes a first functional unit block (FUB) coupled to the graphics accelerator, and a second FUB coupled... | 02/20/2007 |
| 7176930 | Reducing fill and improving quality of interlaced displays using multi-sampling The present invention provides a system, method and computer program product for reducing fill and improving quality of interlaced displays using multi-sampling. In an embodiment of the invention, a frame buffer for a interlaced display is filled. Initially, a first... | 02/13/2007 |
| 7173970 | Methods and apparatus for decoding and displaying multiple digital images in parallel Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode H... | 02/06/2007 |
| 7146444 | Method and apparatus for prioritizing a high priority client A method and apparatus of deprioritizing a high priority client. An isochronous data stream request is generally referred to as a “high priority” client. These high priority requests are sensitive to time, such that a certain amount of data must be retrieved wit... | 12/05/2006 |
