Did You Know...
...that in 1800 ether was first used by partyers as a fun diversion? Sniffing the gas led to hilarious and raucous laughter as people watched each other become more and more intoxicated and silly. Several doctors independently realized the value ether would have to anesthetize surgery patients. Of those who claimed rights to the "discovery," none had a happy ending. One had a seizure and died defending his rights. Another spent his life in an asylum because he had been denied acclaim. A third became addicted to chloroform and, in a New York City jail, he soaked a cloth in the drug, severed an artery and bled to death.
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| Number | Title | Issue Date |
| 8174531 | Programmable graphics processor for multithreaded execution of programs A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for stori... | 05/08/2012 |
| 8174530 | Parallel date processing apparatus A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array for processing data relating to graphical primitives. Vertex data relating to graphical primitives is used as feedback data for the processin... | 05/08/2012 |
| 8169440 | Parallel data processing apparatus A method of processing data relating to geometrical primitives is disclosed. Each of the primitives has a plurality of vertices. The method uses a plurality of processing elements in parallel with one another, and comprises assigning respective vertex data to the pr... | 05/01/2012 |
| 8169441 | Method and system for minimizing an amount of data needed to test data against subarea boundaries in spatially composited digital video A method and system for minimizing an amount of data needed to test data against subarea boundaries in spatially composited digital video is provided. Graphics data for a frame is composed of geometry chunks. Each geometry chunk is defined by its own bounding region... | 05/01/2012 |
| 8154553 | Centralized streaming game server Exemplary embodiments include an interception mechanism for rendering commands generated by interactive applications, and a feed-forward control mechanism based on the processing of the commands on a rendering engine, on a pre-filtering module, and on a visual encod... | 04/10/2012 |
| 8139069 | Method and system for improving data coherency in a parallel rendering system A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method for managing a plurality of independently processed texture streams in a parallel rendering system... | 03/20/2012 |
| 8134563 | Computing system having multi-mode parallel graphics rendering subsystem (MMPGRS) employing real-time automatic scene profiling and mode control A parallel graphics rendering system is embodied within a host computing system and includes a plurality of graphic processing pipelines (GPPLs) and graphics processing modules. The parallel graphics rendering system supports one or more modes of parallel operation ... | 03/13/2012 |
| 8130228 | System and method for processing low density parity check codes using a deterministic caching apparatus A system, method and article of manufacture are disclosed for processing Low Density Parity Check (LDPC) codes. The system comprises a multitude of processing units for processing the codes; and a processor chip including an on-chip, multi-port data cache for tempor... | 03/06/2012 |
| 8125487 | Game console system capable of paralleling the operation of multiple graphic processing units (GPUS) employing a graphics hub device supported on a game console board A game console system capable of parallelizing the operation of multiple graphics processing units (GPUs) supported on game console board, using a graphics hub device, and a multi-mode parallel graphics rendering subsystem supporting multiple modes of parallel opera... | 02/28/2012 |
| 8106913 | Graphical representation of load balancing and overlap Circuits, methods, and apparatus for graphically displaying performance metrics of processors such as graphics processing units in multiple processor systems. Embodiments of the present invention may provide metric information regarding operations in alternate-frame... | 01/31/2012 |
| 8106912 | Parallel image processing system control method and apparatus To reduce the required amount of program codes when processing the whole image in a one-dimensional SIMD parallel image processing system having a smaller number of PEs than the number of pixels in the width direction of the image to be processed. A controller for c... | 01/31/2012 |
| 8098252 | Parallel video processing architecture The video data is parallel processed allowing for extremely fast video processing or a greatly reduced clock requirement for the video processing circuit. In operation, each video channel reads from main memory. This allows each video channel to track the laser dire... | 01/17/2012 |
| 8094157 | Performing an occurence count of radices One embodiment of the present invention sets forth a technique for efficiently performing a radix sort operation on a graphics processing unit (GPU). The radix sort operation is conducted on an input list of data using one or more passes of a series of three process... | 01/10/2012 |
| 8085272 | Method and system for improving data coherency in a parallel rendering system A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of receiving a common input stream, tracking a periodic event associated... | 12/27/2011 |
| 8085273 | Multi-mode parallel graphics rendering system employing real-time automatic scene profiling and mode control A multi-mode parallel 3-D graphics system having multiple graphics processing pipelines with multiple GPUs supporting a parallel graphics rendering process having time, frame and object division modes of operation, wherein each GPU comprises video memory, a geometry... | 12/27/2011 |
| 8081191 | Multimedia processing in parallel multi-core computation architectures In a media server for processing data packets, media server functions are implemented by a plurality of modules categorized by real-time response requirements. ... | 12/20/2011 |
| 8077181 | Adaptive load balancing in a multi processor graphics processing system Systems and methods for balancing a load among multiple graphics processors that perform different portions of a rendering task. A rendering task is partitioned into portions for each of two (or more) graphics processors. The graphics processors perform their respec... | 12/13/2011 |
| 8072460 | System, method, and computer program product for generating a ray tracing data structure utilizing a parallel processor architecture A system, method, and computer program product are provided for generating a ray tracing data structure utilizing a parallel processor architecture. In operation, a global set of data is received. Additionally, a data structure is generated utilizing a parallel proc... | 12/06/2011 |
| 8068109 | Processor task and data management Task and data management systems methods and apparatus are disclosed. A processor event that requires more memory space than is available in a local storage of a co-processor is divided into two or more segments. Each segment has a segment size that is less than or ... | 11/29/2011 |
| 8059128 | Apparatus and method for performing blit operations across parallel processors A method of performing a blit operation in a parallel processing system includes dividing a blit operation into batches of pixels, performing reads of pixels associated with a first batch in any order, confirming that all reads of pixels associated with the first ba... | 11/15/2011 |
| 8049760 | System and method for vector computations in arithmetic logic units (ALUs) The present disclosure describes implementations for processing instructions and data across multiple Arithmetic Logic Units (ALUs). In one implementation, a graphics processing apparatus comprises a plurality of ALUs configured to process independent instructions i... | 11/01/2011 |
| 8022957 | Apparatus and method for processing data A data processing apparatus includes a plurality of processing units each performing a respective one of process parts into which a predetermined process to be performed on data is divided, and a changing unit that changes a connection between the plurality of proce... | 09/20/2011 |
| 8004532 | Server apparatus and server control method in computer system A server apparatus and a server control method which transmits display data to a client apparatus and which displays the display data on a display screen of the client apparatus, wherein there are provided a plurality of accelerators, each of the plurality of accele... | 08/23/2011 |
| 7961194 | Method of controlling in real time the switching of modes of parallel operation of a multi-mode parallel graphics processing subsystem embodied within a host computing system A method of controlling the mode of parallel operation of a multi-mode parallel graphics processing system (MMPGPS) embodied within a host computing system having (i) host memory space (HMS) for storing one or more graphics-based applications and a graphics library ... | 06/14/2011 |
| 7944450 | Computing system having a hybrid CPU/GPU fusion-type graphics processing pipeline (GPPL) architecture A computing system capable of parallelizing the operation of multiple graphics processing units (GPUs) supported on a hybrid CPU/GPU fusion-architecture chip and/or on an external graphics card, and employing a multi-mode parallel graphics rendering subsystem having... | 05/17/2011 |
| 7940274 | Computing system having a multiple graphics processing pipeline (GPPL) architecture supported on multiple external graphics cards connected to an integrated graphics device (IGD) embodied within a bridge circuit A computing system capable of parallelizing the operation of multiple graphics processing units (GPUs) supported on an integrated graphic device (IGD) embodied within a bridge circuit, and employing a multi-mode parallel graphics rendering subsystem having software ... | 05/10/2011 |
| 7924287 | Method and system for minimizing an amount of data needed to test data against subarea boundaries in spatially composited digital video A method and system for minimizing an amount of data needed to test data against subarea boundaries in spatially composited digital video. Spatial compositing uses a graphics unit or pipeline to render a portion (subarea) of each overall frame of digital video image... | 04/12/2011 |
| 7907143 | Interactive debugging and monitoring of shader programs executing on a graphics processor A development application leverages the programmability of shader execution units in the graphics processing subsystem to make graphics processing subsystem state data accessible to applications executed outside the graphics processing subsystem. The development app... | 03/15/2011 |
| 7889202 | Transparent multi-buffering in multi-GPU graphics subsystem This invention discloses a method and system for implementing transparent multi-buffering in multi-GPU graphics subsystems. The purpose of multi-buffering is to reduce GPU idle time. In one example, after rendering a first image by a first GPU in a back buffer, the ... | 02/15/2011 |
| 7852340 | Scalable shader architecture A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preve... | 12/14/2010 |
| 7843457 | PC-based computing systems employing a bridge chip having a routing unit for distributing geometrical data and graphics commands to parallelized GPU-driven pipeline cores supported on a plurality of graphics cards and said bridge chip during the running of a graphics application A PC-based computing system employing a bridge chip with a routing unit to distribute geometrical data and graphics commands to multiple GPU-driven pipeline cores supported on a plurality of graphics cards and the bridge chip. The PC-based computing system includes ... | 11/30/2010 |
| 7830390 | Color computation of pixels using a plurality of vertex or fragment shader programs A plurality of vertex or fragment processors on a graphics processor perform computations. Each vertex or fragment processor is capable of executing a separate program to compute a specific result. A combiner manages the combination of the results from the respectiv... | 11/09/2010 |
| 7812845 | PC-based computing system employing a silicon chip implementing parallelized GPU-driven pipelines cores supporting multiple modes of parallelization dynamically controlled while running a graphics application A PC-based computing system employing a silicon chip implementing parallelized GPU-driven pipelines cores supporting multiple modes of parallelization dynamically controlled while running a graphics application. The PC-based computing system includes system memory f... | 10/12/2010 |
| 7812844 | PC-based computing system employing a silicon chip having a routing unit and a control unit for parallelizing multiple GPU-driven pipeline cores according to the object division mode of parallel operation during the running of a graphics application A PC-based computing system employing a silicon chip having a routing unit and a control unit for parallelizing multiple GPU-driven pipeline cores according to an object division mode of parallel operation, during the running of a graphics application. The PC-based ... | 10/12/2010 |
| 7812843 | Distributed resource architecture and system A distributed resource system comprises a plurality of compute resource units operable to execute graphics applications and generate graphics data, and a plurality of visualization resource units communicatively coupled to the plurality of compute resource units and... | 10/12/2010 |
| 7804504 | Managing yield for a parallel processing integrated circuit A method for manufacturing an integrated circuit is described. The integrated circuit comprises a plurality of tiles, each tile comprising a processor and a switch coupled to neighboring tiles to form a network of tiles. The method includes identifying at least one ... | 09/28/2010 |
| 7800620 | Optimizing automated shader program construction Although GPUs have been harnessed to solve non-graphics problems, these solutions are not widespread because GPUs remain difficult to program. Instead, an interpreter simplifies the task of programming a GPU by providing language constructs such as a set of data typ... | 09/21/2010 |
| 7782327 | Multiple parallel processor computer graphics system An accelerated graphics processing subsystem that significantly increases the processing speed of computer graphics commands. The preferred embodiment of this invention presents a first-of-its-kind graphics processing subsystem that combines the processing power of ... | 08/24/2010 |
| 7782325 | Motherboard for supporting multiple graphics cards The invention provides a motherboard that uses a high-speed, scalable system bus such as PCI Express® to support two or more high bandwidth graphics slots. The lanes from the motherboard chipset may be directly routed to two or more graphics slots. For instance, th... | 08/24/2010 |
| 7782326 | Parallel video processing architecture The video data is parallel processed allowing for extremely fast video processing or a greatly reduced clock requirement for the video processing circuit. In operation, each video channel reads from main memory. This allows each video channel to track the laser dire... | 08/24/2010 |
