Bizarre Patents
Combination Beverage Container and Spittoon
A combination beverage container and spittoon includes a bottom portion including outer wall and a first inner wall defining a spittoon space.
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| Number | Title | Issue Date |
| 8013763 | Method and apparatus for unit interval calculation A method is provided. In this method, a clock signal and an input signal are received, where the input signal is a Manchester encoded signal. A unit interval (UI) number is incremented for each UI received upon receipt of a valid UI. The UI number is compared to a p... | 09/06/2011 |
| 7924181 | System, method, and computer program product for digitally estimating a clock signal associated with an audio signal A system, method, and computer program product are provided for estimating a clock signal. Specifically, during use, a clock signal associated with an audio signal is digitally estimated. ... | 04/12/2011 |
| 7876242 | Method and apparatus for unit interval calculation of displayport auxilliary channel without CDR A method for decoding a Manchester-II encoded DISPLAYPORT compatible signal is provided. In this method, several counters are reset. A unit interval (UI) counter is incremented for each UI received upon receipt of a valid UI, and the value of the UI counter is compa... | 01/25/2011 |
| 7667627 | Memory code generator The invention provides a memory code generator. In one embodiment, the memory code generator comprises a code memory, a preparation buffer set, and a correlation buffer set. The code memory stores code data. The preparation buffer set retrieves a first code segment ... | 02/23/2010 |
| 7633414 | Circuit and method for Manchester decoding with automatic leading phase discovery and data stream correction A method and circuit are shown for decoding a Manchester encoded data input signal, wherein preamble found, data input, and recovered clock signals are received and a phase of the data input signal stored responsive thereto. A decision time signal alternates state r... | 12/15/2009 |
| 7541949 | Receiving device and tire pressure monitoring system A receiving device is provided. A pulse width is measured, it is selected whether a determination process is performed for a pulse width having the length of one bit in accordance with the measured value of the pulse width or a pulse width having the length of ½ bi... | 06/02/2009 |
| 7498959 | Apparatus and method of wideband decoding to synthesize a decoded excitation signal with a generated high frequency band signal Encoding and/or decoding a wideband signal produces high frequency band spectra from low frequency band spectral information. Linear prediction filter coefficients are determined for the entire wideband spectrum of an input signal. An energy value in each of a plura... | 03/03/2009 |
| 7373574 | Semiconductor testing apparatus and method of testing semiconductor A semiconductor testing apparatus, includes a test signal generating unit that generates a test signal corresponding to a test pattern to output the generated test signal to a device under test (DUT); a comparison signal generating unit that generates a comparison s... | 05/13/2008 |
| 7358871 | Method and system for decoding data A system and method for decoding a received data stream is disclosed. The method includes detecting first and second data transitions of a received data stream. Each of the data transitions is of a first transition type (e.g. rising or falling transition). The time ... | 04/15/2008 |
| 7342519 | Receiving device and tire pressure monitoring system A receiving device is provided. A pulse width is measured, it is selected whether a determination process is performed for a pulse width having the length of one bit in accordance with the measured value of the pulse width or a pulse width having the length of ½ bi... | 03/11/2008 |
| 7323943 | PLL circuit with deadlock detection circuit Disclosed is a PLL circuit including a deadlock detection circuit includes a counter circuit for counting a clock signal. In a deadlock state, the deadlock detection circuit outputs a deadlock detection signal responsive to an output signal from the counter circuit ... | 01/29/2008 |
| 7320082 | Power control system for synchronous memory device A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is ove... | 01/15/2008 |
| 7289048 | Duo-binary encoder and optical duo-binary transmission apparatus using the same A duo-binary encoder performs a parallel processing and an optical duo-binary transmission apparatus using the encoder to enhance transmission capability. The duo-binary encoder has a judgment unit for judging whether an odd number or even number of ‘0’s exists ... | 10/30/2007 |
| 7279950 | Method and system for high frequency clock signal gating A differential clock signal gating method and system is provided, wherein a clock buffer circuit control path develops a clock gating signal with a timing relationship to a clock signal. The clock gating signal gates a buffer on the clock buffer circuit controlled p... | 10/09/2007 |
| 7245238 | Method and apparatus for data encoding A method and apparatus for data encoding such as 3 to 4 encoding (base64, uuencode etc.) is provided. Bytes of data to be encoded having negative values are made positive while preserving the information to be encoded. The positive values may be manipulated by addit... | 07/17/2007 |
| 7199728 | Communication system with low power, DC-balanced serial link A data communication system comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a set... | 04/03/2007 |
| 7193539 | Precoder and optical duo-binary transmission apparatus using the same A precoder for an optical duo-binary transmission apparatus disposing the precoder before a time division multiplexer includes a judgment unit for judging whether an odd number or even number of ‘1’s exist in data input signals of N channels inputted at an n | 03/20/2007 |
| 7161992 | Transition encoded dynamic bus circuit A transition encoded dynamic bus includes an encoder circuit at the input to the bus and a decoder circuit at the output to the bus. The encoder circuit generates a signal indicative of a transition at the input to the bus rather than the actual value at the input. ... | 01/09/2007 |
| 7133482 | Decoding method and Manchester decoder A method and a corresponding decoder for decoding a Manchester encoded binary data signal includes receiving the Manchester encoded binary data signal having a first sequence of central bit transitions and a second sequence of initial bit transitions. A local clock ... | 11/07/2006 |
| 7123171 | RFID readers and RFID tags communicating using extensible bit vectors RFID system components, such as readers and tags, communicate by transmitting and receiving a wave that conveys a bit stream. Informing signals, such as special bits, are inserted in the stream between words. An informing signal indicates whether a certain word is t... | 10/17/2006 |
| 7123678 | RZ recovery A data and clock recovery system adapted for use with RZ data. In one embodiment a phase detector provides phase information for low to high data signal transitions only. In another embodiment a clock recovered from rising transitions is mixed with a clock recovered... | 10/17/2006 |
| 7099965 | Network device interface for digitally interfacing data channels to a controller a via network The present invention provides a network device interface and method for digitally connecting a plurality of data channels to a controller using a network bus. The network device interface interprets commands and data received from the controller and polls the data ... | 08/29/2006 |
| 7098833 | Tri-value decoder circuit and method A tri-value decoder and method for decoding at least three states of an input signal are provided. An exemplary tri-value decoder and method can facilitate decoding of input signals without the use of threshold values and/or forcing a tri-state input signal to a mid... | 08/29/2006 |
| 7096285 | Network device interface for digitally interfacing data channels to a controller via a network The present invention provides a network device interface and method for digitally connecting a plurality of data channels, such as sensors, actuators, and subsystems, to a controller using a network bus. The network device interface interprets commands and data rec... | 08/22/2006 |
| 7088270 | Low power, DC-balanced serial link A receiver for a data communication system which comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence... | 08/08/2006 |
| 7058737 | Network device interface for digitally interfacing data channels to a controller via a network The present invention provides a network device interface and method for digitally connecting a plurality of data channels, such as sensors, actuators, and subsystems, to a controller using a network bus. The network device interface interprets commands and data rec... | 06/06/2006 |
| 7057538 | 1/N-rate encoder circuit topology An encoder circuit and a related method for its operation, in which digital encoding, such as differential phase-shift keyed (DPSK) encoding, is performed as a parallel operation on N bits at a time. Each encoded bit is both output in parallel with the others of the... | 06/06/2006 |
| 7030786 | RFID readers and RFID tags communicating using extensible bit vectors RFID system components, such as readers and tags, communicate by transmitting and receiving a wave that conveys a bit stream. Informing signals, such as special bits, are inserted in the stream between words. An informing signal indicates whether a certain word is t... | 04/18/2006 |
| 6999011 | Microcode driven adjustment of analog-to-digital converter Microcode driven adjustment of analog scaling of an analog signal prior to being provided to an analog-to-digital converter. The microcode also causes the system to read the resulting digital value, and determine whether the scaling value should be adjusted for that... | 02/14/2006 |
| 6987824 | Method and system for clock/data recovery for self-clocked high speed interconnects A method and system is provided for clock/data recovery for self-clocked high speed interconnects. A data signal is received and then equalized. The equalized data signal then provides the trigger to separate “ones” and “zeros” one-shots. The equalized Manch... | 01/17/2006 |
| 6963295 | Method of recovering and decoding of Manchester coded data A method and apparatus for accurately decoding a Manchester data stream having transition time distortion and noise spikes. Briefly, in an embodiment using a protocol where a falling edge at the mid-point of a bit represents a “1” bit and a rising edge at the mi... | 11/08/2005 |
| 6961396 | Digital banking circuit A digital blanking circuit allows a first digital input signal transition to be passed on to a following stage, but prohibits the passing of subsequent transitions for a predetermined blanking interval. One embodiment of the present invention employs rising edge and... | 11/01/2005 |
| 6928158 | Transmission of a clock by a capacitive isolating barrier A method and a circuit for regenerating a clock signal based on a flip-flop and on two complementary signals at the clock rate, the flip-flop being assembled as a divider by two of a combination of shaping signals each translating a direction, respectively rising or... | 08/09/2005 |
| 6909386 | Duo-binary encoder and optical duo-binary transmission apparatus An optical duo-binary transmission apparatus using an optical duo-binary transmission method is disclosed. The apparatus includes a duo-binary encoder that performs parallel processing. The duo-binary encoder includes a level change detection unit for detecting that... | 06/21/2005 |
| 6839006 | Communication device An S/P converter 120 converts input data from serial to parallel for every two bits in different timings, thereby outputting two types of parallel data. Based on the input data, a timing detector 130 detects a timing which corresponds to boundaries bet... | 01/04/2005 |
| 6833799 | Ultra low power adaptive pulse distance ratio decoder for coded data by feedback of output data A pulse decoder for decoding digitally coded data, each data bit being represented by a coding scheme consisting of a combination of short and long duration pulses having a predetermined interrelationship. The decoder has an input for receiving an input signal defin... | 12/21/2004 |
| 6774824 | Encoding device and method for encoding digital image improved by requantization of a predetermined subbit plane There is provided a digital image encoding device which can enhance image compression performance while maintaining an image quality. When coefficient bits are decomposed/aligned in four encoded paths for each context by a procedure called coefficient bit modeling o... | 08/10/2004 |
| 6768433 | Method and system for decoding biphase-mark encoded data A method and system for decoding a biphase-mark input stream is disclosed. Aspects of the present invention include receiving an external biphase-mark input stream by a receiver module; recovering timing information from the input stream; decoding the input stream t... | 07/27/2004 |
| 6721376 | Signal encoding for transmission of multiple digital signals over single physical medium Two or more digital signals are encoded using two or more respective line codes. The line codes are chosen in conjunction with the data rates of the digital signals such that the encoded signals are substantially orthogonal to each other in the frequency domain. As ... | 04/13/2004 |
| 6646576 | System and method for processing data Methods and systems for processing data are disclosed. An exemplary system for parsing and modifying data stored in an array of storage elements includes a parsing system configured to access the data stored in selected storage elements of the array of st... | 11/11/2003 |
