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| Number | Title | Issue Date |
| 7825838 | Capacitor rotation method for removing gain error in sigma-delta analog-to-digital converters A method for removing component mismatch errors for a system parameter being set by a ratio of two or more physical, electrical components (“components”) of the same kind on an integrated circuit including providing an array of component units having the same co... | 11/02/2010 |
| 7821436 | System and method for reducing power dissipation in an analog to digital converter A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and... | 10/26/2010 |
| 7683814 | Constant current source, ramp voltage generation circuit, and A/D converter A ramp voltage generation circuit suitable for an A/D converter preventing a variation in a digital value obtained by an A/D conversion operation. The circuit comprises a stabilization voltage source Vref, an operation amplifier AMP1 having a non-inversion in... | 03/23/2010 |
| 7671770 | Single pass INL trim algorithm for networks A single-pass method of trimming a network, and a network manufactured according to the method, uses the assumption that the peak INL value is minimized by trimming all the structures in the network to a same target value based upon the boundary conditions of the di... | 03/02/2010 |
| 7468686 | Systems and methods for providing compact digitally controlled trim of multi-segment circuits A trimdac circuit for adjusting the output of a digital-to-analog converter (DAC) is provided. The trimdac may be used to adjust a plurality of resistor segments in the DAC. The trimdac may include a programmable Read Only Memory (ROM) or other suitable memory devic... | 12/23/2008 |
| 7414559 | Dynamic bias circuit A bias circuit includes a digital to analog converter (D2A) generating an output representing a voltage level for tuning an analog signal. The D2A is coupled to a primary register frame that is one of a plurality of register frames forming a data chain... | 08/19/2008 |
| 7382153 | On-chip resistor calibration for line termination A circuit for calibrating a resistance value on an integrated circuit includes a resistor network, a reference voltage generator, a comparator, a servo loop, and a shift register. The resistor network includes a plurality of resistor and switch pairs in parallel. Th... | 06/03/2008 |
| 7363186 | Apparatus and method for self calibration of current feedback The current drawn by a precision resistor that is selectively connected across a load is utilized to calibrate a current sensed by current sensing device that is connected in series with the load. ... | 04/22/2008 |
| 7352230 | Internal voltage trimming circuit for use in semiconductor memory device and method thereof An internal power voltage trimming circuit and its method individually or simultaneously perform level trimming for a plurality of power voltages in a semiconductor memory device. The internal power voltage trimming circuit includes a trimming control signal generat... | 04/01/2008 |
| 7348907 | Range compression in oversampling analog-to-digital converters An analog-to-digital converter according to the invention is provided. The analog-to-digital converter preferably includes an analog input signal, a first reference signal, a second reference signal, and a range compression signal. The range compression signal is pr... | 03/25/2008 |
| 7333383 | Fuse resistance read-out circuit Methods and apparatus for a more precise readout of fuse resistance than a conventional binary readout are provided. For some embodiments, a digital readout of fuse resistance may be obtained by selectively altering an effective reference resistance to which the fus... | 02/19/2008 |
| 7324031 | Dynamic bias circuit A bias circuit includes a digital to analog converter (D2A) generating an output representing a voltage level for tuning an analog signal. The D2A is coupled to a primary register frame that is one of a plurality of register frames forming a data chain. The pluralit... | 01/29/2008 |
| 7310266 | Semiconductor device having memory cells implemented with bipolar-transistor-antifuses operating in a first and second mode A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing inform... | 12/18/2007 |
| 7295057 | Methods and apparatus for characterizing electronic fuses used to personalize an integrated circuit An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the f... | 11/13/2007 |
| 7292167 | Apparatus for error compensation of self calibrating current source An apparatus for error compensation of a self calibrating current source adapted for compensating errors of at least one self calibrating current source. The compensation apparatus includes an imitative self calibrating current source, a current source reference app... | 11/06/2007 |
| 7280415 | Flash memory device and method of repairing defects and trimming voltages A memory device includes a nonvolatile memory cell array including a plurality of memory cells with a portion of the memory cells to store fuse data, and a fuse register to store the fuse data from the memory cell array. An operation of the memory device is modified... | 10/09/2007 |
| 7272523 | Trimming for accurate reference voltage A method for trimming reference voltage circuitry includes defining a desired target reference voltage for a set of at least one die. At least two reference voltages are measured for at least two different trim settings associated with a given die of the at least on... | 09/18/2007 |
| 7259703 | Device for recording laser trim progress and for detecting laser beam misalignment The device for detecting and tracking a status of a device under laser trim includes: a series connected string of trim tracking links; and a plurality of detecting devices wherein each detecting device is coupled in parallel with a corresponding trim tracking link.... | 08/21/2007 |
| 7221191 | Signal samplers with enhanced dynamic range Signal sampler embodiments are provided for processing input signals along signal paths in response to mode-command signals. They include a follower transistor with a control terminal and a current terminal that establish at least part of a signal path. They also in... | 05/22/2007 |
| 7215142 | Multi-stage inverse toggle An inverse toggle circuit includes a pair of input connections for receiving each of four possible input signal combinations in a sequential rotational manner. Each of four data paths are defined to be exercised in accordance with a respective input signal combinati... | 05/08/2007 |
| 7209060 | Reducing variation in reference voltage when the load varies dynamically Providing a substantially constant reference voltage to a component from a reference buffer connected by a path. The load that would be offered to the reference buffer in desired durations is estimated, and a dummy load is added to the path such that the aggregate l... | 04/24/2007 |
| 7177610 | Calibrated low-noise current and voltage references and associated methods A low-noise current reference circuitry includes a voltage source, a current source, and a controller. The voltage source generates a reference voltage. The current source provides a low-noise output current in response to a control signal. The controller provides t... | 02/13/2007 |
| 7148827 | Offset compensating apparatus and method of digital/analog converter An offset compensating apparatus and method of a digital/analog converter that are capable of preventing an offset of a driving unit by switching an offset generated from an LCD panel driving unit of an LCD projection TV, by adding a current cell of the least signif... | 12/12/2006 |
| 7116255 | Multiplying digital to analog converter and multipath pipe line analog to digital converter using the same A multiplying digital to analog converter comprising a digital to analog converter having a plurality of capacitors coupled in parallel, applying first signals to the capacitors during a sampling period, and applying second signals to the capacitors during an amplif... | 10/03/2006 |
| 7109901 | Use of and gates with a write control circuit for trimming a bleeder resistor In a semiconductor integrated circuit, serially inputted trimming data are sequentially written to plural memory cells in accordance with selection signals for trimming a bleeder resistor, making it possible to dispense with a data register for storing the trimming ... | 09/19/2006 |
| 7100067 | Data transmission error reduction via automatic data sampling timing adjustment A data transmission error reduction circuit is formed including a delay circuit, a detection circuit and a control circuit. In one embodiment, the delay circuit includes n delay element and multiplexor pairs, selectively employable to apply an aggregate amount of ti... | 08/29/2006 |
| 7093151 | Circuit and method for providing a precise clock for data communications An apparatus comprising a circuit configured to (i) generate an output having a frequency and (ii) adjust the frequency in response to a measured duration of a known time interval associated with an input data stream. ... | 08/15/2006 |
| 7084792 | Circuit for zero offset auto-calibration and method thereof A circuit for zero offset auto-calibration and a method thereof suitable for video signal analog-to-digital converters are provided. The circuit is connected between the last stage of a pipeline analog-to-digital converter (the pipeline ADC) and a differential signa... | 08/01/2006 |
| 7081842 | Electronic component value trimming systems Described is a system for trimming the value of an electronic component. The system comprises: at least one trimming component, each trimming component having an associated switch for selectively connecting that trimming component to the electronic component in resp... | 07/25/2006 |
| 7049986 | Fuse link trim algorithm for minimum residual A parameter of an integrated circuit including a first trim array and a second trim array is trimmed by measuring an initial value of the parameter, determining whether the parameter exceeds a reference value, and as long as the parameter exceeds the reference value... | 05/23/2006 |
| 7049985 | Method and circuit for producing trimmed voltage using D/A converter circuit Trimming by disconnecting a fuse connected in parallel to a feedback resistor of an amplifier circuit would cause a variation in voltage value due to a remaining resistance component. A voltage generator circuit is provided therein with a D/A converter circuit of an... | 05/23/2006 |
| 7031683 | Apparatus and methods for calibrating signal-processing circuitry A calibration circuitry includes an adjustable capacitor, a voltage generator, a reference voltage generator, and a controller. The reference voltage generator provides a reference voltage. The voltage generator provides a measurement voltage that depends on the cap... | 04/18/2006 |
| 7031218 | Externally clocked electrical fuse programming with asynchronous fuse selection Embodiments are provided in which a method and an apparatus for sequentially programming electrical fuses are described. A fuse pointer is advanced to point to (i.e., select) the fuses sequentially. When the fuse pointer reaches (i.e., points to) a fuse that is not ... | 04/18/2006 |
| 7030728 | Layout and method to improve mixed-mode resistor performance A resistor layout and method of forming the resistor are described which achieves improved resistor characteristics, such as resistor stability and voltage coefficient of resistance. A resistor is formed from a conducting material such as doped silicon or polysilico... | 04/18/2006 |
| 7015845 | Digital to analog converter system A control arrangement and method includes a digital to analog converter and a mode controller that is operative to provide the digital to analog converter with a plurality of reference voltage ranges (Vref) under a respective plurality of operating modes. ... | 03/21/2006 |
| 6999020 | Semiconductor integrated circuit A frequency detecting circuit 10 detects frequency of a sampling pulse SP, and outputs the detected frequency as a detection value VOUT. A current adjusting circuit 20 adjusts a power supply current Ivd to be supplied to an AD converter 30 in ac... | 02/14/2006 |
| 6956518 | Method and apparatus for subclocking a SAR analog-to-digital converter Method and apparatus for subclocking a SAR analog-to-digital converter. A method is disclosed for clocking the operation of a SAR analog-to-digital converter (ADC). A low frequency clock and a high frequency clock are provided. An analog input voltage is then tracke... | 10/18/2005 |
| 6946920 | Circuit for locking an oscillator to a data stream An apparatus comprising a control circuit and a first circuit. The first circuit may be configured to generate a calibration signal in response to an adjustment signal and a first control signal. The control circuit may be configured to generate (i) the first contro... | 09/20/2005 |
| 6919833 | Parallel converter topology for reducing non-linearity errors A parallel DAC topology reduces systematic linearity errors by offsetting the digital codes inputted to the individual DACs from one another. Linearity errors that would normally add together are thus reduced. ... | 07/19/2005 |
| 6882292 | Analog to digital converter with bandwidth tuning circuit A pipelined analog to digital converter. Each stage in the pipeline has a flash converter and a multiplying digital to analog converter. Each stage provides a digital bits and an analog residue that is passed to the next stage in the pipeline. The digital bits from ... | 04/19/2005 |
