Bizarre Patents
Behavior Modification Wristwatch
A wristwatch including a watch band and a watch body having an octagon shaped perimeter and being red in color and having the word STOP thereon to resemble a stop sign.
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| Number | Title | Issue Date |
| 8184027 | Semiconductor device and differential amplifier circuit therefor A differential amplifier circuit comprising a differential amplifier capacitor and a mismatch error cancellation circuitry, a first pair of capacitors, a second pair of capacitors consisting of switching network. The switching network is arranged to operate in a fir... | 05/22/2012 |
| 8174417 | System and a method of correcting baseline wander A system and method of correcting baseline wander (BLW) are disclosed. An analog-to-digital converter (ADC) converts an analog input to a digital output, and a slicer maps the digital output to one of a plurality of predefined values. A BLW correction unit generates... | 05/08/2012 |
| 8174416 | Automatic common-mode rejection calibration The present invention relates to a circuit and a method for automatic common-mode rejection calibration in a differential conversion system and unbalance compensation for balancing the operation point of a circuit in the signal path and for enhancing the common-mode... | 05/08/2012 |
| 8164496 | Mismatch compensators and methods for mismatch compensation In a compensator for compensating mismatches, and in methods for such compensation, the compensator compensates for mismatches in output signals of a system with mismatches during normal operation of the system with mismatches. The compensator comprises: a mismatch ... | 04/24/2012 |
| 8164495 | Integrated non-linearity (INL) and differential non-linearity (DNL) correction techniques for digital-to-analog converters (DACS) INL values are determined for a plurality of sub-segments of a DAC that is adapted to accept N bit digital input codes, and a first set of correction codes that can be used to reduce to a range of INL values (to thereby improve linearity of the DAC) are determined a... | 04/24/2012 |
| 8164494 | Method and device for digitally correcting DC offset There is provided a digital Direct Current (DC) offset correction method and device. The device includes a digital-analog converter charging a load capacitor according to an input code value and generating an initial voltage value of the load capacitor; a comparator... | 04/24/2012 |
| 8159377 | System, method, and circuitry for blind timing mismatch estimation of interleaved analog-to-digital converters A timing skew estimation system is disclosed that includes a plurality of interleaved analog-to-digital converter circuits (ADCs), a timing mismatch estimation unit, and a correction unit. The timing mismatch estimation unit calculates a correlation between each of ... | 04/17/2012 |
| 8144040 | Randomization of sample window in calibration of time-interleaved analog to digital converter A technique that randomizes a sample window over which one or more interleave mismatch corrections are made to a time interleaved analog to digital converter (TIADC). ... | 03/27/2012 |
| 8134485 | Device for converting analog signal into digital values and correcting the values An analog to digital converting device has a first converter nonlinearly converting an analog level into a first digital value every first sampling period, shorter than a second sampling period, with low precision, a second converter linearly converting the analog l... | 03/13/2012 |
| 8125359 | Analog-to-digital converter According to an embodiment, an analog-to-digital converter (ADC) including an ADC unit, a clock-phase control unit, a multiplexer, and a digital-output processing unit is provided. The digital-output processing unit inputs digital outputs of the ADC unit to either a... | 02/28/2012 |
| 8120517 | Digital-analog conversion circuit and output data correction method of the same A digital-analog conversion circuit includes a correction unit that adds a correction bit to a lower-order bit of externally input first digital input data and outputs second digital input data, and a conversion unit that receives the second digital input data and o... | 02/21/2012 |
| 8085175 | Linearizer The present invention provides an advanced adaptive predistortion linearization technique to dramatically reduce nonlinear distortion in power amplifiers over a very wide instantaneous bandwidth (up to 2 GHz) and over a wide range of amplifier types, input frequenci... | 12/27/2011 |
| 8085174 | Current-mode DAC capable of prospective correction A current-mode DAC includes at least one to-be-corrected one current source, a referential current source, a current comparator for comparing the current of the to-be-corrected current source and the current of the referential current source, a correction controller... | 12/27/2011 |
| 8072360 | Simultaneous sampling analog to digital converter The invention is a novel scheme of performing an analog to digital conversion of simultaneous sampled analog inputs using multiple sample and hold circuits and a single successive approximation analog to digital converter (“SAR ADC”). Each of the analog inputs a... | 12/06/2011 |
| 8068044 | Correction circuit for D/A converter There is provided a correction circuit for a D/A converter, comprising: a constant current source to be connected between high- and low-potential power source lines for supplying a power source voltage to the D/A converter; and a current controller which is adapted ... | 11/29/2011 |
| 8063802 | Filter for adjusting ADC samples Phase is adjusted by using an analog to digital converter to convert an analog signal to a plurality of digital samples. A filter is used to filter the plurality of digital samples to obtain a plurality of phase adjusted samples. ... | 11/22/2011 |
| 8063803 | Calibration of offset, gain and phase errors in M-channel time-interleaved analog-to-digital converters Techniques for correcting component mismatches in an M-channel time-interleaved Analog to Digital Converter (ADC). In order to obtain an error measure for offset, gain or phase, errors, outputs from each ADC are either summed or averaged over No samples. ... | 11/22/2011 |
| 8059019 | Method and system for minimizing the accumulated offset error for an analog to digital converter A method and system utilized with an analog to digital converter is disclosed. The method and system comprise providing a first conversion on an input signal. In the first conversion, an offset error is added to the input signal to provide a first result. The method... | 11/15/2011 |
| 8040263 | Analog-to-digital converter with a calibration function An analog-to-digital converter includes a reference voltage generator that outputs a reference voltage, a first comparator and a second comparator that compare the reference voltage and a voltage of an input signal and output a digital signal having a first logical ... | 10/18/2011 |
| 8040264 | Pipeline analog to digital converter and a residue amplifier for a pipeline analog to digital converter A pipeline analog to digital converter comprising: a first analog to digital converter for determining a first part of an analog to digital conversion result, and for forming a residue signal; an amplifier for amplifying the residue signal, the amplifier including a... | 10/18/2011 |
| 8031091 | Reception circuit, method of creating AD converter conversion table of reception circuit, and signal transfer system A reception circuit includes: an AD converter that outputs digital data in accordance with an input signal; a correction circuit that corrects nonlinearity of the AD converter; and an equalization circuit that equalizes the corrected digital data, wherein the correc... | 10/04/2011 |
| 8022847 | Signal processing device A signal processing device, even when a steep difference in DC level is included in a signal read from a disc such as a DVD-RAM format, cuts off the DC level and pulls the read signal into an appropriate A/D input level. A steep difference in DC level between a data... | 09/20/2011 |
| 8018360 | Systems and methods for mitigating latency in a data detector feedback loop Methods and systems for mitigating latency in a data detector feedback loop are included. For example, a method for reducing latency in an error corrected data retrieval system is included. The method includes performing an analog to digital conversion at a sampling... | 09/13/2011 |
| 8009070 | Compensation of mismatch errors in a time-interleaved analog-to-digital converter A method for the compensation of frequency-response mismatch errors in M-channel time-interleaved ADCs. The compensation is done through an M-periodic time-varying filter hn(k)=hn mod M(k) (2), or, equivalently, a set of M time-invariant filter... | 08/30/2011 |
| 7999706 | Characteristic acquisition device, method and program It is possible to reduce errors generated between multiple D/A conversion paths. A characteristic acquisition device includes [1] an arbitrary signal generator that converts a first (second) input digital pattern into a first (second) output analog pattern, [2] a di... | 08/16/2011 |
| 7999707 | Apparatus for compensating for error of time-to-digital converter An apparatus for compensating for an error of a time-to-digital converter (TDC) is disclosed to receive a delay phase from a phase detector including the TDC and a phase error including a TDC error and compensate for the TDC error to have a time resolution higher by... | 08/16/2011 |
| 7999708 | Analog correction of a phase-mismatch in high-sample rate time-interleaved analog-to-digital converters A method of phase mismatch correction in high-sample rate time-interleaved analog-to-digital converters (ADC) is provided. An ADC parallel array has an output signal that is processed by a phase-mismatch detector. The detector drives a clock generator control circui... | 08/16/2011 |
| 7994952 | Converter, conversion method, program, and recording medium Provided is a highly accurate converter and the like that makes up for the instability of circuit elements, by focusing on a relationship between the Markov chain and β conversion. A converter 1 that determines the decoded value of a sample value x based on ... | 08/09/2011 |
| 7990298 | Reduction of digital-to-analog converter distortion using constellation rotation A method for signal conversion includes generating a complex digital signal, which includes digital In-phase (I) and Quadrature (Q) components, for conversion into respective analog I and Q components by first and second Digital-to-Analog Converters (DACs). A distor... | 08/02/2011 |
| 7986253 | Method and apparatus for digital error correction for binary successive approximation ADC An apparatus for digital error correction in a successive approximation (SAR) analog to digital converter (ADC) includes a binary weighted digital to analog converter (DAC) which can be virtually divided into multiple sub-DACs for redundancy insertion; and a compara... | 07/26/2011 |
| 7973686 | Integrated circuit device and electronic instrument An integrated circuit device includes a plurality of data line driver circuits, a first correction D/A conversion circuit, and a plurality of D/A conversion circuits. Each of the data line driver circuits includes an operational amplifier, an input capacitor, and a ... | 07/05/2011 |
| 7973685 | Method and apparatus for filtering digital signals Methods, and other embodiments associated with signal filtering are described. According to one embodiment, an apparatus includes an analog-to-digital converter that generates a first digital component and a second digital component from an analog signal. A filter f... | 07/05/2011 |
| 7973684 | Self auto-calibration of analog circuits in a mixed signal integrated circuit device Auto-calibration of the analog circuits occurs when requested by a user and/or the occurrence of an event(s). The user may invoke an auto-calibration on demand through an auto-calibration (ACAL) input to the mixed-signal integrated circuit. An external vo... | 07/05/2011 |
| 7969334 | Apparatus for correcting setting error in an MDAC amplifier Multiplying digital-to-analog converters (MDACs), which are generally employed in pipelined analog-to-digital converters (ADCs), can have a settling error associated with the MDAC amplifier. Here, a circuit is provided that includes additional amplifiers and a capac... | 06/28/2011 |
| 7961123 | Time-interleaved analog-to-digital converter A time-interleaved (TI) analog-to-digital converter (ADC) is provided. The TI ADC generally comprises a clock generator, two or more ADCs, adjustable delay elements, and an estimator. The clock generator generates clock signals. Each ADC is associated with at least ... | 06/14/2011 |
| 7952502 | Imbalance and distortion cancellation for composite analog to digital converter (ADC) Imbalance and distortion cancellation for composite analog to digital converter (ADC). Such an ‘ADC’ is implemented using two or more ADCs may be employed for sampling (e.g., quantizing, digitizing, etc.) of an analog (e.g., continuous time) signal in accordance... | 05/31/2011 |
| 7952501 | Demodulator capable of compensating offset voltage of RF signal and method thereof A demodulator capable of compensating for an offset voltage of a radio frequency (RF) signal, and a method of compensating for the offset voltage of the RF signal are provided. The demodulator includes an analog-to-digital conversion (ADC) unit for converting a firs... | 05/31/2011 |
| RE42387 | Method for compensating non-linearity of a sigma-delta analog-to-digital converter The invention concerns a method for compensating the non-linearity of a sigma-delta analog-to-digital converter (A2) with quantization at N levels comprising a digital-to-analog converter (24). The method comprises a calibrating step which consists in ... | 05/24/2011 |
| 7944379 | SAR ADC and method with INL compensation An apparatus for analog-to-digital conversion using successive approximation is provided. There is a successive approximation register or SAR controller for providing a digital code representing a conversion result, and an integral non-linearity (INL) compensator co... | 05/17/2011 |
| 7944378 | Circuits and methods for calibrating analog and digital circuits In one embodiment the present invention includes a circuit for calibrating analog and digital circuits. The circuit includes an analog input stage, a discrete time processing stage, a DAC, and a calibration circuit. The analog input stage includes an input resistanc... | 05/17/2011 |
