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"What, sir, would you make a ship sail against the wind and currents by lighting a bonfire under her deck? I pray you, excuse me, I have not the time to listen to such nonsense."
Napoleon Bonaparte ; When told of the Robert Fulton steamboat
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| Number | Title | Issue Date |
| 4727268 | Logic circuitry having two programmable interconnection arrays According to this invention a plurality of kinds of circuit blocks is formed as a circuit block area on a chip substrate to have a desired logic function. An array of signal output wires and array of signal input wires are formed adjacent the circuit bloc... | 02/23/1988 |
| 4684830 | Output circuit for a programmable logic array An output circuit (50) is provided for a programmable logic array (PLA) integrated circuit. The output circuit (50) includes a flip flop (52) which stores a given output term from the array. The flip flop (52) contains a set input lead (S) and a reset inp... | 08/04/1987 |
| 4677437 | Input signal switching matrix for an elevator In this invention, "column" buses connected to a power supply and "row" input lines are arranged in the shape of a matrix, external signal lines are connected to the intersection points thereof, and the "column" buses are switched at predetermined cycles ... | 06/30/1987 |
| 4675556 | Binomially-encoded finite state machine A finite state machine suitable for MOS fabrication is described. The finite state machine includes a programmed logic array (PLA). The PLA AND plane includes logical inputs and state signal inputs. The state signal inputs are decoded binomially. The stat... | 06/23/1987 |
| 4661922 | Programmed logic array with two-level control timing A programmed logic array (PLA) is equipped with a first master-slave shift register on the intermediate wordlines (e.g., W1, W2 . . . Wn) between AND and OR planes of the PLA and a second master-slave shift register on the... | 04/28/1987 |
| 4617479 | Programmable logic array device using EPROM technology The programmable logic array device basically comprises a programmable AND array (FIGS. 5, 11) having a plurality of memory cells (30, 31) arranged in addressable rows (40-45) and columns (32-38) and which can be individually programmed to contain logic d... | 10/14/1986 |
| 4554640 | Programmable array logic circuit with shared product terms A programmable array logic circuit is provided having a programmable AND gate array and having means for connecting individual AND gate outputs to the input of one or the other of a pair of neighboring OR gates. This allows the product terms to be shared ... | 11/19/1985 |
| 4504904 | Binary logic structure employing programmable logic arrays and useful in microword generation apparatus Binary logic structure is described which requires less space on an integrated circuit chip. This structure includes an encode programmable logic array responsive to a first group of binary input signals for producing a smaller number of binary signals wh... | 03/12/1985 |
| 4488230 | Programmed logic array with external signals introduced between its AND plane and its OR plane A combinational logic device, such as an AND gate, is connected to control the flow of information along a wordline from the AND plane to the OR plane of a PLA (programmed logic array). To each such combinational logic device is applied an input signal fr... | 12/11/1984 |
| 4488229 | PLA-Based finite state machine with two-level control timing and same-cycle decision-making capability A PLA (e.g., 100) operates with two-level clock control timing, that is, with a pair of master and slave registers (e.g., 12 and 13) connected to the PLA wordlines (e.g., W1, W2, . . . Wn) between the PLA's AND and OR plan... | 12/11/1984 |
| 4488246 | Integrated logic network with simplified programming An electrically programmable logic network having an AND matrix, and OR matrix, and interfact circuits for inputting, outputting, and making connections between the matrices. To simplify programming of the matrices and to effect programming simultaneously... | 12/11/1984 |
| 4422072 | Field programmable logic array circuit A field-programmable logic array (FPLA) circuit of both the single level logic type containing a programmable AND/NAND gate array and the multiple level logic type containing a programmable OR/NOR gate array responsive to data from a programmable AND/NAND... | 12/20/1983 |
| 4415818 | Programmable sequential logic circuit devices The programmable sequential logic circuit device is constructed to sequentially form an output signal to an external circuit and the circuit state for the next operation in accordance with input signals applied from outside and the internal state of the c... | 11/15/1983 |
| 4313106 | Electrically programmable logic array Two matrix arrays comprised of Gate Injected Metal Oxide Semiconductor (GIMOS) non-volatile memory elements. Interconnection is made via inverters to form an electrically Alterable Programmable Logic Array (ALPLA).... | 01/26/1982 |
| 4307379 | Integrated circuit component An integrated circuit component having an array of rows and columns of programmable coupling elements, the rows being coupled to a plurality of independent input signals and the columns being coupled to output ports through a plurality of selectors. With ... | 12/22/1981 |
| 4206507 | Field programmable read only memories A field-programmable read only memory which is programmed by means of flying-lead connections, and which is therefore easily re-programmed. The device can be provided with interface circuits such as relays and opto-couplers to provide a compact and versat... | 06/03/1980 |
| 4180744 | Energy management system An energy management system for limiting continuously instantaneous permissible power level of a plurality of controllable loads including a transducer device for generating an output signal when the measured instantaneous power level exceeds a pre-set in... | 12/25/1979 |
| 4034243 | Logic array structure for depletion mode-FET load circuit technologies A depletion mode load device structure is disclosed which improved upon the existing Weinberger layout technique, as applied to enhancement mode/depletion mode circuitry. The structure of an FET, self biased load device includes a single metallized vertic... | 07/05/1977 |
| 3956745 | Programmable keyboard arrangements A programmable keyboard of the kind in which a member presents a plurality of discrete areas to a co-operating probe, each of which areas produces a unique signal when addressed by the probe, is provided with a liquid crystal display to identify the curre... | 05/11/1976 |
