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Dionysius Lardner, Professor of Natural Philosophy and Astronomy at University College, London ; 1830
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| Number | Title | Issue Date |
| 8183934 | PLL circuit and voltage-controlled oscillator In a PLL circuit, a threshold discriminator generates a control signal indicating a relative level of a control voltage. A controller outputs a controlling value based on the control signal. If the control signal indicates a high level when the controlling value spe... | 05/22/2012 |
| 8044722 | Oscillation frequency control circuit To provide a highly stable oscillation frequency control circuit wherein the frequency thereof is corrected, an adequate range of the input levels of external reference signals is determined in accordance with temperature characteristics in detecting the external re... | 10/25/2011 |
| 7755436 | PLL apparatus Provided is a PLL apparatus outputting a frequency signal from a voltage-controlled oscillation unit in synchronization with an external reference frequency signal, in which the fluctuation of the frequency is reduced even when the external reference signal has a tr... | 07/13/2010 |
| 7667545 | Automatic calibration lock loop circuit and method having improved lock time A lock loop circuit (216) includes a precharge circuit (304), an oscillator circuit (306), and a calibration circuit (309). The calibration circuit includes at least one register (362). The precharge circuit provides a precharge si... | 02/23/2010 |
| 7586378 | Method and system for using a frequency locked loop logen in oscillator systems Aspects of a method and system for using a frequency locked loop LOGEN in oscillator systems may include generating an oscillating signal via one or more circuits comprising a feedback loop. The generation may be controlled by enabling or disabling the feedback loop... | 09/08/2009 |
| 7538620 | Phase lock control system for a voltage controlled oscillator A phase lock control system is presented for controlling a voltage controlled oscillator. The system includes a voltage controlled oscillator that produces a frequency signal exhibiting an output frequency that varies dependent upon the value of a control voltage ap... | 05/26/2009 |
| 7486146 | Loop system capable of auto-calibrating oscillating frequency range and related method A loop system capable of auto-calibrating an oscillating frequency range includes a frequency error detector, a voltage controlled oscillator (VCO), a voltage input unit, and a switch. The frequency error detector includes a rotational frequency detector, a state ma... | 02/03/2009 |
| 7463097 | Systems involving temperature compensation of voltage controlled oscillators Systems involving temperature compensation of voltage controlled oscillators are provided. In this regard, a representative system incorporates: a voltage controlled oscillator (VCO) having a tuning port and a phase-locked loop (PLL); and a temperature dependent vol... | 12/09/2008 |
| 7439813 | Method and system for generating carrier frequencies for UWB application Apparatus and method for generating first, second and third carrier frequencies of 3432 MHz, 3960 MHz and 4488 MHz respectively, for use in a wireless transmission system deploy only first and second PLLs which are configured to generate 6336 MHz and 2640 MHz signal... | 10/21/2008 |
| 7436263 | Apparatus and method for presenting a modulated output signal at an output locus An apparatus that presents an output signal that is modulated by input signal includes: (a) A signal source providing a signal at a reference frequency. (b) A frequency comparer coupled with the signal source and the output signal for comparing the extant output sig... | 10/14/2008 |
| 7420427 | Phase-locked loop with a digital calibration loop and an analog calibration loop A phase-locked loop (PLL) architecture (100) is provided that includes a voltage-controlled oscillator (VCO) (116). The PLL architecture (100) also includes a digital calibration loop (132) coupled to the VCO (116). The digital cal... | 09/02/2008 |
| 7408415 | Voltage controlled oscillator phase locked loop circuit with loop filter capacitance tuning A phase locked loop circuit comprises a voltage controlled oscillator with a control input to which a variable control voltage is applied and a phase-frequency discriminator with an output connected to a loop filter to produce the control voltage. To provide the pha... | 08/05/2008 |
| 7391273 | Clock signal output apparatus and control method of same, and electric apparatus and control method of same The clock signal output device has a crystal oscillator for generating a reference clock signal and generating and outputting an output clock signal having a prescribed frequency on the basis of the reference clock signal. The device also has an atomic oscillator fo... | 06/24/2008 |
| 7388437 | System and method for tuning a frequency synthesizer An apparatus for generating an output signal having a particular frequency includes an oscillator, a first tuning module, and a second tuning module. The oscillator generates an output signal associated with an output frequency. When coupled to the oscillator, the f... | 06/17/2008 |
| 7382201 | Signal generating apparatus and method thereof A signal generating apparatus is disclosed for generating a synthesized signal according to an input signal, the signal generating apparatus includes a phase-locked loop device for generating the synthesized signal; a control unit for controlling the control signal ... | 06/03/2008 |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7372339 | Phase lock loop indicator A phase-locked loop (PLL) circuit includes a power-on-reset (POR) to reset a digital block and set an initial input voltage value VCTRL of voltage-controlled oscillator (VCO). An input divider and a feedback divider are provided to set the frequency ratio of output ... | 05/13/2008 |
| 7366931 | Memory modules that receive clock information and are placed in a low power state Embodiments described herein provide a power saving state for a memory system. For example, a memory system may derive clocking information from a training pattern sent over a memory channel. A memory may comprise a link to receive training frames, and circuitry to ... | 04/29/2008 |
| 7362826 | Receiver including an oscillation circuit for generating an image rejection calibration tone A receiver circuit includes an oscillator circuit configured to generate a calibration tone and a phase locked loop (PLL) reference signal. An output frequency of the VCO may be divided by respective amounts to derive a desired calibration tone frequency and a desir... | 04/22/2008 |
| 7358783 | Voltage, temperature, and process independent programmable phase shift for PLL A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability f... | 04/15/2008 |
| 7356111 | Apparatus and method for fractional frequency division using multi-phase output VCO A phase-locked loop (PLL) frequency synthesizer capable of being tuned in small step sizes. The PLL frequency synthesizer includes a PLL circuit. A phase-locked loop (PLL) frequency synthesizer includes a PLL core and a feedback frequency divider. The PLL core recei... | 04/08/2008 |
| 7353011 | Method and apparatus for operating a PLL for synthesizing high-frequency signals for wireless communications A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitanc... | 04/01/2008 |
| 7352557 | Vertical capacitor apparatus, systems, and methods An apparatus and system, as well as fabrication methods therefor, may include a plurality of vertically-oriented plates separated by dielectric layers, wherein the vertically-oriented plates include a plurality of terminals coupled to a bottom side of the plates. | 04/01/2008 |
| 7352250 | Phase locked loop circuits, offset PLL transmitters, radio frequency integrated circuits and mobile phone systems A PLL circuit equipped with a loop gain detecting circuit that can suppress the change of the loop gain. When detecting the loop gain, the frequency of the input signal to the second input (IN-2) of the phase detector is first changed, and the response corres... | 04/01/2008 |
| 7336147 | Inductance variable device A inductance variable device includes a first inductor, a second inductor magnetically coupled to the first inductor, a current source whose current is variable, electrically connected to the first inductor, and a current control unit. The current control unit contr... | 02/26/2008 |
| 7332940 | Voltage hold circuit and clock synchronization circuit A voltage hold circuit which holds an input signal voltage includes a voltage comparator unit configured to output a result of comparison between a voltage of an externally inputted control signal and a voltage of an outputted analog hold signal, a digital value hol... | 02/19/2008 |
| 7323914 | Charge pump circuit Adverse effects of switching noise produced by a charge pump circuit on a displayed image are prevented. In a synchronizing separation circuit 18, a synchronizing signal is separated from a video signal. The separated synchronizing signal is subjected to ½ f... | 01/29/2008 |
| 7323944 | PLL lock management system A PLL includes a charge pump, a loop filter, a VCO, and a calibration unit. The calibration unit performs coarse tuning to select one or multiple frequency ranges, performs fine tuning to determine an initial control voltage that puts the VCO near a desired operatin... | 01/29/2008 |
| 7321735 | Optical down-converter using universal frequency translation technology A method and system for converting an optical signal to electrical information signals, including demodulated baseband information signals and modulated baseband signals at multiple harmonics. In an embodiment, the optical information signal is amplitude modulated w... | 01/22/2008 |
| 7317360 | Fractional-N synthesizer system and method A fractional-N synthesizer system including a plurality of fractional-N synthesizers all updated to simultaneously generate an output frequency from the same reference frequency, a phase locked loop having an output signal whose frequency is a fractional multiple of... | 01/08/2008 |
| 7317778 | Phase-locked loop control circuit An electrical circuit is disclosed, which comprises a phase locked loop (PLL) circuit and a PLL start-up circuit configured to selectively provide a reference signal to the phase locked loop circuit based upon relative frequencies of an input signal to the phase loc... | 01/08/2008 |
| 7315214 | Phase locked loop A phase locked loop includes a controlled oscillator for delivering an output signal at a determined output frequency, and a variable frequency divider for converting the output signal into a signal at divided frequency. The PLL is termed composite in that it includ... | 01/01/2008 |
| 7312663 | Phase-locked loop having a bandwidth related to its input frequency An integrated circuit includes a phase-locked loop (PLL) in which the loop bandwidth of the PLL is proportional to the input frequency of the PLL. The PLL includes a phase/frequency detector (PFD), a charge pump, a loop filter, and a voltage-controlled oscillator (V... | 12/25/2007 |
| 7301414 | PLL circuit, radio-communication equipment and method of oscillation frequency control A Phase-Locked Loop (PPL) circuit includes a voltage controlled oscillator (VCO), a reference signal oscillator, first and second frequency dividers, a phase comparator, a charge pump and a loop filter. The VCO has a plural number of oscillation frequency boards and... | 11/27/2007 |
| 7301416 | Semiconductor integrated circuit for wireless communication A semiconductor integrated circuit with a PLL (Phase Locked Loop) built therein is used in a semiconductor integrated circuit for wireless communication. The PLL circuit generates an oscillation signal having a predetermined frequency, which is combined with a recei... | 11/27/2007 |
| 7295826 | Integrated frequency translation and selectivity with gain control functionality, and applications thereof Methods and apparatuses for frequency selectivity and frequency translation, and applications for such methods and apparatuses, are described herein. The method includes steps of filtering an input signal, and down-converting the filtered input signal. The filtering... | 11/13/2007 |
| 7292835 | Wireless and wired cable modem applications of universal frequency translation technology Frequency translation and applications of same are described herein, including cable modem applications. Such applications include, but are not limited to, frequency down-conversion, frequency up-conversion, enhanced signal reception, unified down-conversion and fil... | 11/06/2007 |
| 7288973 | Method and apparatus for fail-safe resynchronization with minimum latency A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and v... | 10/30/2007 |
| 7289051 | Digital-to-analog converters including charge pumps and related automatic laser power control devices and methods A digital-to-analog converter may include a clock signal generator and a charge pump. The clock signal generator may be configured to generate an information clock signal responsive to a digital input signal so that different duty cycles of the information clock sig... | 10/30/2007 |
| 7288975 | Method and apparatus for fail-safe and restartable system clock generation A method and apparatus for fail-safe and restartable system clock generation provides recovery from failures due to incorrect clock generator settings or from marginal clock distribution components. Clock failure is detected at a point along the clock distribution p... | 10/30/2007 |
