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| Number | Title | Issue Date |
| 8085098 | PLL circuit A PLL circuit comprising an oscillation unit, a frequency division unit, a phase comparison unit, and a generation unit comprises a switching unit that switches between a first state in which a control voltage output from the generation unit is input into the oscill... | 12/27/2011 |
| 8018289 | Holdover circuit for phase-lock loop A clock circuit includes a phase-lock loop and a holdover circuit. The phase-lock loop generates an output clock signal having a constant frequency based on a loop filter voltage of a loop filter in the phase-lock loop. The holdover circuit generates and stores a di... | 09/13/2011 |
| 7932784 | Frequency and phase locked loop synthesizer The present invention is a frequency and phase locked loop (FPLL) synthesizer having a frequency-locked loop (FLL) operating mode and a phase-locked loop (PLL) operating mode. The FLL operating mode is used for rapid coarse tuning of the FPLL synthesizer and is foll... | 04/26/2011 |
| 7746179 | Method and apparatus for selecting a frequency generating element A method and apparatus for selecting an optimum VCO from an array of VCOs is disclosed. Each VCO in the array has an output range and a limit. In one embodiment, a search set of VCOs is designated as all VCOs in a system. The limit is compared to a tuning value whic... | 06/29/2010 |
| 7737792 | Phase Locked loop circuit and semiconductor integrated circuit device using the same To provide a phase locked loop circuit that is capable of performing an automatic adjustment that satisfies a desired characteristic not depending on a process variation and an environmental variation. The phase locked loop circuit has a phase frequency comparator, ... | 06/15/2010 |
| 7443257 | Mechanical oscillator control electronics A control system for a mechanical oscillator having a sinusoidal drive signal with a frequency that is a fractional multiple of a frequency of a signal of the mechanical oscillator. The drive signal may be in phase and in registration with the signal from the mechan... | 10/28/2008 |
| 7420427 | Phase-locked loop with a digital calibration loop and an analog calibration loop A phase-locked loop (PLL) architecture (100) is provided that includes a voltage-controlled oscillator (VCO) (116). The PLL architecture (100) also includes a digital calibration loop (132) coupled to the VCO (116). The digital cal... | 09/02/2008 |
| 7411464 | Systems and methods for mitigating phase jitter in a periodic signal An oscillator circuit can generate a periodic signal, and a frequency adjustment circuit can adjust the frequency of the periodic signal. The periodic signal may include phase jitter. In one aspect of the invention, the phase jitter may be mitigated by connecting ot... | 08/12/2008 |
| 7408415 | Voltage controlled oscillator phase locked loop circuit with loop filter capacitance tuning A phase locked loop circuit comprises a voltage controlled oscillator with a control input to which a variable control voltage is applied and a phase-frequency discriminator with an output connected to a loop filter to produce the control voltage. To provide the pha... | 08/05/2008 |
| 7372875 | Systems and methods for synchronization in asynchronous transport networks Techniques for synchronizing the clock of a local telecommunications network connected to a remote clock source through an asynchronous transport network such as an Ethernet metropolitan area transport network. A basic holdover loop for retaining the current reconst... | 05/13/2008 |
| 7372337 | Voltage controlled oscillator comprising an injection pulling compensation circuit The present invention relates to a method for stabilising the operation of a voltage controlled oscillator driven by a phase locked loop, the voltage controlled oscillator delivering an RF signal and receiving through at least one spurious path a harmonic component ... | 05/13/2008 |
| 7365581 | Regulated adaptive-bandwidth PLL/DLL using self-biasing current from a VCO/VCDL A PLL/DLL circuit is current self-biased responsive to a current Ild provided from a voltage regulator to a VCO or VCDL. Bias current Ibias, which is proportional to Ild, is provided to components of the PLL/DLL, such as a charge pum... | 04/29/2008 |
| 7366271 | Clock and data recovery device coping with variable data rates A clock and data recovery (CDR) device is disclosed that is capable of recovering a clock signal from a data signal that has a variable data rate. The CDR device includes a reference clock generating section for dividing a basic clock by a first predetermined value ... | 04/29/2008 |
| 7362826 | Receiver including an oscillation circuit for generating an image rejection calibration tone A receiver circuit includes an oscillator circuit configured to generate a calibration tone and a phase locked loop (PLL) reference signal. An output frequency of the VCO may be divided by respective amounts to derive a desired calibration tone frequency and a desir... | 04/22/2008 |
| 7355482 | Methods and apparatus for compensating a variable oscillator for process, voltage, and temperature variations using a replica oscillator Circuits and methods for compensating a variable oscillator for process and/or operational variations. The circuit generally comprises (a) a replica oscillator, (b) a counter configured to count pulses of the replica oscillator and to produce a count signal, and (c)... | 04/08/2008 |
| 7353011 | Method and apparatus for operating a PLL for synthesizing high-frequency signals for wireless communications A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitanc... | 04/01/2008 |
| 7348823 | Delay circuit and delay synchronization loop device A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay uni... | 03/25/2008 |
| 7342460 | Expanded pull range for a voltage controlled clock synthesizer A technique provides a clock source that meets accuracy requirements, allows the use of a low cost resonator, provides a wide range of output frequencies, and provides suitable phase noise performance. The technique generates a clock signal having a target output fr... | 03/11/2008 |
| 7336756 | Reprogrammable bi-directional signal converter A signal converter is comprised of a plurality of counters (“macro-counters”). In turn, each of the macro-counters is comprised of a plurality of single-bit counters (“micro-counters”) that are adapted to receive configuration data in the form of bit fields.... | 02/26/2008 |
| 7336548 | Clock generating circuit with multiple modes of operation A clock generating circuit includes a phase comparison circuit that generates a delay control signal corresponding to the relative phases of an output clock signal and a reference clock signal. A voltage controlled delay circuit generates the delayed clock signal by... | 02/26/2008 |
| 7327196 | Fast switching phase lock loop (PLL) device and method A fast switching phase lock loop (PLL) device is provided. The PLL has a voltage controlled oscillator that generates a signal at a frequency according to a received voltage. A memory holds a set of adjustment values, with each adjustment value set to cause the VCO ... | 02/05/2008 |
| 7327172 | Integrated clock generator with programmable spread spectrum using standard PLL circuitry An apparatus comprising a phase lock loop circuit and a control circuit. The phase lock loop circuit configured to generate an output signal having a first frequency in response to (i) an input signal having a second frequency, (ii) a first divider value and (iii) a... | 02/05/2008 |
| 7327173 | Delay-locked loop having a pre-shift phase detector A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock ... | 02/05/2008 |
| 7323942 | Dual loop PLL, and multiplication clock generator using dual loop PLL To provide dual loop PLLs capable of reducing the lock-up time in the initial start-up, and multiplication clock generators contributing to reduction of the power dissipation. The dual loop PLL comprises a dual loop PLL having a phase comparison loop having a phase ... | 01/29/2008 |
| 7323916 | Methods and apparatus for generating multiple clocks using feedback interpolation A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. ... | 01/29/2008 |
| 7317361 | Ensemble oscillator and related methods An ensemble clock comprises: an input for receiving a reference signal; multiple free-running oscillators each configured to generate a corresponding free-running frequency; an output oscillator configured to generate a controlled frequency having a frequency respon... | 01/08/2008 |
| 7315218 | Method and apparatus to center the frequency of a voltage-controlled oscillator A circuit and method are provided for calibrating an analog oscillator in the digital domain. The circuit and method disclosed herein centers an oscillation frequency of an analog oscillator by producing a binary signal to which the analog oscillator is responsive. ... | 01/01/2008 |
| 7310020 | Self-biased phased-locked loop In general, in one aspect, the disclosure describes a phase-locked loop circuit. The circuit includes an oscillator having a first control input, a second control input, and a third control input, wherein the first control input, the second control input, and the th... | 12/18/2007 |
| 7310024 | High stability double oven crystal oscillator A double oven crystal oscillator (DOCXO) is disclosed which is highly stable by incorporating means to reduce the effects of ambient pressure changes on the frequency of the oscillator. The oscillator crystal is mounted in a temperature controlled inner oven to redu... | 12/18/2007 |
| 7304545 | High latency timing circuit A phase locked loop (PLL) circuit, comprises a frequency integrator circuit that receives a target signal, a phase shift signal and a frequency gain correction parameter and that selectively disables tracking frequency offset based on a value of the frequency gain c... | 12/04/2007 |
| 7301404 | Method and apparatus for transceiver frequency synthesis A method and apparatus for frequency synthesis in a transceiver are based on providing a primary frequency synthesizer configured to synthesize a receiver frequency signal from a receiver reference frequency signal, and providing an offset frequency synthesizer conf... | 11/27/2007 |
| 7301414 | PLL circuit, radio-communication equipment and method of oscillation frequency control A Phase-Locked Loop (PPL) circuit includes a voltage controlled oscillator (VCO), a reference signal oscillator, first and second frequency dividers, a phase comparator, a charge pump and a loop filter. The VCO has a plural number of oscillation frequency boards and... | 11/27/2007 |
| 7302026 | Clock recovery circuit and electronic device using a clock recovery circuit A clock recovery circuit includes a phase discriminating circuit for discriminating, at every edge of a received data signal, phase lead or phase lag of an identically directed edge of the clock signal, and outputting the phase discrimination signal; an edge detecti... | 11/27/2007 |
| 7295077 | Multi-frequency clock synthesizer A phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal, a phase detector circuit coupled to receive the timing reference signal, a controllable oscillator circuit controlled according to an output of the phase detector circuit, a... | 11/13/2007 |
| 7288998 | Voltage controlled clock synthesizer A voltage controlled clock synthesizer includes a phase-locked loop (PLL) circuit that receives a timing reference signal, a controllable oscillator circuit, such as a VCO, providing an oscillator output signal, and a feedback divider circuit coupled to the oscillat... | 10/30/2007 |
| 7288975 | Method and apparatus for fail-safe and restartable system clock generation A method and apparatus for fail-safe and restartable system clock generation provides recovery from failures due to incorrect clock generator settings or from marginal clock distribution components. Clock failure is detected at a point along the clock distribution p... | 10/30/2007 |
| 7283801 | Circuit arrangement for phase locked loop, and phase locked loop based method to be used in cellular network terminals The invention relates to a circuit arrangement (4) for a PLL to be used in a terminal (50) of a time division cellular network. In a PLL according to the invention, the control voltage (32a) to a VCO (33) in the PLL is kept at a de... | 10/16/2007 |
| 7279988 | Digital frequency locked loop and phase locked loop frequency synthesizer A frequency synthesizer including frequency and phase locked loop that operates in either a frequency locked loop (FLL) mode or a phase locked loop (PLL) mode. In a first state, the frequency and phase locked loop operates in the FLL mode for initial frequency acqui... | 10/09/2007 |
| 7277503 | Apparatus and method for synchronizing sampling frequency and carrier frequency in a multi-carrier communication system An apparatus and method for synchronizing sampling frequencies of a receiver and a transmitter of a multi-carrier communication system is provided. The receiver includes an estimator for estimating a frequency offset by employing an additional angle rotation of a re... | 10/02/2007 |
| 7277519 | Frequency and phase correction in a phase-locked loop (PLL) In one embodiment, a system for frequency and phase correction in a phase-locked loop (PLL) includes a phase frequency detector, first and second charge pumps respectively generating a first current and a voltage, a voltage-to-current (V2I) converter, a current summ... | 10/02/2007 |
