Bizarre Patents
Combination Beverage Container and Spittoon
A combination beverage container and spittoon includes a bottom portion including outer wall and a first inner wall defining a spittoon space.
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| Number | Title | Issue Date |
| 8248104 | Phase comparator and phase-locked loop A phase comparator is provided that solves the problem that a VCO cannot be controlled with high precision. A frequency divider frequency-divides a VCO signal applied as input to an input terminal (10) in steps, and supplies the VCO signals of each step as ou... | 08/21/2012 |
| 7999577 | Apparatus and method for detecting a changing point of measured signal Provided is an apparatus comprising a delaying section that generates a plurality of delayed signals by delaying a single first input signal by different delay amounts; a first acquiring section that acquires each of a plurality of input second input signals at a fi... | 08/16/2011 |
| 7463069 | Phase detector with selection of differences between input signals Known phase detectors have feedbackloops and do not function properly under severe conditions. By providing said phase detectors with difference establishers (1) for establishing differences between input signals and with selectors (2) for selecting on... | 12/09/2008 |
| 7443251 | Digital phase and frequency detector Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a p... | 10/28/2008 |
| 7423456 | Fast response time, low power phase detector circuits, devices and systems incorporating the same, and associated methods A circuit for quickly accomplishing highly accurate phase detection using low power is described. The circuit includes a phase decision circuit that receives two clock signals and detects the phase relationship between the two signals by determining which signal was... | 09/09/2008 |
| 7417470 | Phase frequency detector with a novel D flip flop Methods, systems and components for use with or as a phase frequency detector. The phase frequency detector stretches its output pulse, allowing the detector to operate in a more linear region. As part of the invention, a new configuration for a D type flip flop is ... | 08/26/2008 |
| 7414446 | DLL circuit of semiconductor memory apparatus and method of delaying and locking clock in semiconductor memory apparatus A DLL circuit of a semiconductor memory apparatus includes a frequency sensing unit that generates and outputs a high frequency signal and a low frequency signal on the basis of a CAS latency signal. A clock dividing unit divides the frequency of an internal clock b... | 08/19/2008 |
| 7382163 | Phase frequency detector used in digital PLL system A phase frequency detector includes a phase error detector outputting a phase error signal according to a first input signal and a second input signal; a phase error judgment unit outputting a phase error judgment signal according to the first input signal and the s... | 06/03/2008 |
| 7375557 | Phase-locked loop and method thereof and a phase-frequency detector and method thereof The phase-frequency detector may include a first flip-flop configured to generate a first signal, the first signal transitioning to a first logic level in response to a first edge of a first input signal and transitioning to a second logic level in response to a del... | 05/20/2008 |
| 7372339 | Phase lock loop indicator A phase-locked loop (PLL) circuit includes a power-on-reset (POR) to reset a digital block and set an initial input voltage value VCTRL of voltage-controlled oscillator (VCO). An input divider and a feedback divider are provided to set the frequency ratio of output ... | 05/13/2008 |
| 7359803 | Apparatus and method for measuring parameters of a mixture having solid particles suspended in a fluid flowing in a pipe An apparatus 10,70 and method is provided that includes a spatial array of unsteady pressure sensors 15-18 placed at predetermined axial locations X1-XN disposed axially along a pipe 14 for measuring at least one par... | 04/15/2008 |
| 7355379 | Coaxial type impedance matching device and impedance detecting method for plasma generation A plasma generating method generates plasma in a treating chamber by controlling a high-frequency generating unit to generate a high-frequency signal and by feeding the high-frequency signal to the treating chamber through an impedance matching device. The plasma ge... | 04/08/2008 |
| 7337083 | Process for identification of the direction of rotation of two periodic electrical signals at the same frequency A process and apparatus for identification of the direction of rotation of two periodic electrical signals present on two electrical conductors, particularly of a three-phase power system. In this process, the signals are sampled from two conductors by two wires of ... | 02/26/2008 |
| 7336106 | Phase detector and method having hysteresis characteristics A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the feedback clock signal lags the reference clock signal by more than a seco... | 02/26/2008 |
| 7328624 | Probe for measuring parameters of a flowing fluid and/or multiphase mixture A probe 10,170 is provided that measures the speed of sound and/or vortical disturbances propagating in a single phase fluid flow and/or multiphase mixture to determine parameters, such as mixture quality, particle size, vapor/mass ratio, liquid/vapor ratio, ... | 02/12/2008 |
| 7323946 | Lock detect circuit for a phase locked loop An improved system and method for determining the lock condition of a Phase Locked Loop (PLL) is described. The lock detect circuit generates a fast lock detect signal that may be used to detect a transient loss of lock. The lock detect circuit may also include a ph... | 01/29/2008 |
| 7295640 | Phase detector A phase detector has a reference signal input for a reference signal and a detector input for a signal to be evaluated. A memory unit is connected to the detector input and stores a state of the signal to be evaluated at a storage instant. An evaluation unit is conn... | 11/13/2007 |
| 7282962 | Inverted-phase detector An inverted-phase detector is implemented in a system including a first clock circuit that provides a first clock signal and a delayed clock circuit that outputs an delayed clock signal. A reference circuit outputs a reference signal. A feedback circuit generates a ... | 10/16/2007 |
| 7279938 | Delay chain integrated circuits having binary-weighted delay chain units with built-in phase comparators therein Delay-locked loop integrated circuits include a delay chain having a plurality of delay chain units. The delay chain may be a binary-weighted delay chain and the delay chain units may be arranged in ascending or descending order (e.g., x1, x2, x4, x8, . . . ) accord... | 10/09/2007 |
| 7245540 | Controller for delay locked loop circuits A method of controlling a delay locked loop (DLL) in a memory device is provided. The DLL generates an internal clock signal based on an external clock signal. The DLL constantly responds to variations in operating condition of the memory device to keep the external... | 07/17/2007 |
| 7231009 | Data synchronization across an asynchronous boundary using, for example, multi-phase clocks Additional information on the phase of an external clock signal is obtained by using clock signals to determine if a phase difference between an external clock signal and a first internal sampling clock signal is less than a pre-selected value. If the system determi... | 06/12/2007 |
| 7215418 | Inspection of transparent substrates for defects Methods, apparatus and systems for the detection of defects in transparent substrates such as glass sheets are disclosed. The methods, apparatus and systems are capable of detecting optical path length variations in transparent substrates smaller than 100 nm. ... | 05/08/2007 |
| 7212051 | Control signal generation for a low jitter switched-capacitor frequency synthesizer A phase detector and control signal generator responds to a reference signal and a feedback signal to produce a non-delayed up and down signal. A programmable delay unit delays the non-delayed up and down signal to provide up and down signals for a charge pump. A di... | 05/01/2007 |
| 7162216 | Wireless communication system A wireless communication system, which is provided with a PLL circuit having a plurality of oscillators and is capable of processing two or more transmit and receive signal different in frequency band from one another according to the switching between the oscillato... | 01/09/2007 |
| 7136947 | System and method for automatically synthesizing interfaces between incompatible protocols A system and method for enabling Intellectual Property (IP) Blocks to be reused at a system level. The present invention represents the IP blocks as blocks that exchange messages without needing to represent the functionality of the IP blocks. The implementations of... | 11/14/2006 |
| 7129794 | Phase detector for reducing noise The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference between a first and a second signal, a first circuit adapted to generate a control signal based upon the dete... | 10/31/2006 |
| 7129757 | Clock frequency detect with programmable jitter tolerance An apparatus and method is disclosed for programmable determination of frequency, phase, and jitter relationship of a first clock and a second clock in an electronic system. In a first, initialization, mode, a first register and a second register are initialized wit... | 10/31/2006 |
| 7123069 | Latch or phase detector device The invention relates to a circuit device, into which a first signal and a second signal are input, wherein a first switching array is provided, by means of which it is determined which of the two signals, is the first to change its state. The circuit device may als... | 10/17/2006 |
| 7119839 | High resolution CMOS circuit using a matched impedance output transmission line Image sensor with CMOS output, an another circuit receiving input. The circuit operates like a transmission line, in current mode, with substantially zero voltage. The impedances are matched by setting bias currents. ... | 10/10/2006 |
| 7119583 | Phase detector and method having hysteresis characteristics A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the feedback clock signal lags the reference clock signal by more than a seco... | 10/10/2006 |
| 7109760 | Delay-locked loop (DLL) integrated circuits that support efficient phase locking of clock signals having non-unity duty cycles Delay-locked loop (DLL) integrated circuits include digital phase comparators that are unaffected by variable duty cycle ratios. These phase comparators determine a shortest direction to phase lock before establishing a value of a compare signal (COMP) that specifie... | 09/19/2006 |
| 7110477 | Gaussian frequency shift keying digital demodulator A digital demodulator employing a digital differential detection mechanism based on extracting phase differences directly from the I and Q signals after downconversion to zero-IF and image rejection are performed. The phase of the input I and Q signals is determined... | 09/19/2006 |
| 7109807 | Phase detector for reducing noise The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference between a first and a second signal, a first circuit adapted to generate a control signal based upon the dete... | 09/19/2006 |
| 7102448 | Phase frequency detector used in phase locked loop A phase frequency detector used in a phase locked loop includes a phase error detecting unit for outputting phase error signals according to a phase error between a first input signal and a second input signal, and a reset unit coupled to the phase error detecting u... | 09/05/2006 |
| 7088796 | Phase detector customized for clock synthesis unit A phase detector customized for Clock Synthesis Unit (CSU) is disclosed. The phase detector improves jitter performance by providing minimal activity on VCO control lines and pushing ripple frequency to one octave higher, while maintaining wide linear characteristic... | 08/08/2006 |
| 7072242 | Semiconductor integrated circuit device A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and s... | 07/04/2006 |
| 7053682 | Device and method for clock generation A clock generator includes an interface for receiving a plurality of n periodical signals of the same frequency which are phase-shifted with respect to each other, wherein n/3. Further, a clock signal generator is provided for generating respective clock edges of a ... | 05/30/2006 |
| 7054778 | Method and device for processing analogue output signals from capacitive sensors An analogue output signal of a sensor which comprises a carrier signal with a carrier frequency ωC which is modulated by a measurement size is sampled with a sampling frequency ωA to receive a sampled sensor output signal. The frequency ω | 05/30/2006 |
| 7049852 | Fractional-integer phase-locked loop system with a fractional-frequency-interval phase frequency detector A phase-locked loop circuit has a fractional-frequency-interval phase frequency detector, a charge pump, an oscillator, and a divider. The fractional-frequency-interval phase frequency detector has a phase frequency detector unit that is utilized as or comprises a p... | 05/23/2006 |
| 7046042 | Phase detector A phase detector includes a first flip-flop responsive to a reference clock signal, a first inverter responsive to an output of the first flip-flop, a second flip-flop responsive to a feedback clock signal, a second inverter responsive to an output of the second fli... | 05/16/2006 |
