Did You Know...
...that Robert Adler has the dubious distinction of being the Father of the Couch Potato? Back in 1955 Adler was employed by what was then Zenith Radio Corp., where he was charged to invent something that would allow viewers to turn down the TV volume without leaving their chairs. After a series of flops (such as a wired contraption that people tripped over), Adler hit on the idea of using sound waves. Thus the Remote Control was born...
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| Number | Title | Issue Date |
| 6472908 | Differential output driver circuit and method for same An output circuit is provided which exhibits a waveform having a higher edge rate, with less ringing and power consumption than many conventional differential amplifier output driver circuits. A pre-driver stage using a current-mode logic (CML) design eli... | 10/29/2002 |
| 6462585 | High performance CPL double-gate latch A differential circuit to be used as a latch-up for asymmetric-double-gate complementary metal oxide semiconductor (DGCMOS) devices. The differential circuit includes an asymmetric-DGCMOS device having the weak gates tied to input circuitry and strong gat... | 10/08/2002 |
| 6462587 | Integrated circuit having a comparator circuit including at least one differential amplifier An integrated circuit including a comparator circuit and a vertical voltage control switch element formed on a single substrate. The comparator circuit including a differential amplifier circuit having a current mirror circuit M, a differential amplifier ... | 10/08/2002 |
| 6459306 | Low power differential comparator with stable hysteresis A low power differential comparator wherein the input stage bias is used not only to set a bias level but is also used to set the hysteresis level of the differential comparator circuit. The positive and/or negative inputs to the differential comparator c... | 10/01/2002 |
| 6448822 | Comparator for negative and near-ground signals A comparator circuit that transforms a difference between two input voltage signals into differential branch currents that are independent of the two input voltage signals. In one embodiment, the comparator circuit utilizes an adaptive bias voltage circui... | 09/10/2002 |
| 6445218 | Comparator with offset voltage A comparator according to the present invention can generate an output signal of low or high level by comparing a first and second input voltages that have a common voltage. An input stage circuit of a comparator according to the present invention receive... | 09/03/2002 |
| 6420909 | Comparators A circuit compares a first voltage and a second voltage using a comparator. The comparator has a current divider for dividing a bias current in accordance with the values of the first and second voltages, and for providing two currents. The comparator als... | 07/16/2002 |
| 6411133 | Semiconductor device The differential amplifier of a comparator circuit includes first and second n-type MOSFETs for receiving an input signal, first and second p-type MOSFETs of a current mirror circuit, and a third n-type MOSFET of a current source circuit. The output stage... | 06/25/2002 |
| 6411129 | Logic circuit with output high voltage boost and method of using A differential logic gate providing complimentary input and complimentary output operation. Transistors (50,52) provide the differential input and emitter follower transistors (54,62) provide the complimentary outputs. Enhanced output high logic levels ar... | 06/25/2002 |
| 6411132 | Matched current differential amplifier According to an embodiment of the invention, a circuit is provided that includes a first differential set and a second differential set each having a first and a second input node and a first and a second output node. The first differential set is referen... | 06/25/2002 |
| 6392448 | Common-mode detection circuit with cross-coupled compensation A common-mode detection circuit for measuring a common-mode signal between two complementary signals is disclosed. The common-mode detection circuit includes a first signal divider circuit and a linearizer. The signal divider circuit includes a pair of im... | 05/21/2002 |
| 6392452 | Input buffer circuit for RF phase-locked loops An input buffer circuit includes a first amplifier having low load impedance and a second amplifier having high load impedance. The output signals of the input buffer circuit have wide bandwidth, although the input buffer circuit has two stage amplifiers.... | 05/21/2002 |
| 6392453 | Differential input buffer bias circuit An integrated differential buffer circuit and its method of operation are described in which the buffer circuit has an internal bias line for controlling the supply of voltage to the buffer circuit. When the buffer circuit is first enabled, a start voltag... | 05/21/2002 |
| 6384638 | Differential charge pump for providing a low charge pump current A differential charge pump for providing a low charge pump current. The present invention operates in one embodiment as part of an integrated circuit of a semiconductor chip by providing very small magnitude currents to other on-chip circuitry. Specifical... | 05/07/2002 |
| 6380777 | Output driver having controlled slew rate An off chip driver circuit is adapted to output differential output signals at high speed rate and capable to drive high external loads without degradation of the output signals. Specifically the driver comprises a first differential pair of transistors h... | 04/30/2002 |
| 6377085 | Precision bias for an transconductor A precision bias is provided for a differential transconductor. The precision bias includes a bias circuit, a differential amplifier and a current mirror. The current mirror includes at least two mirror transistors, one of which is connected to the bias c... | 04/23/2002 |
| 6366168 | Efficient ground noise and common-mode suppression network A CMOS differential amplifier is provided comprising a current supply coupled to a first terminal of a power supply. A first CMOS transistor is provided having a first source, a first gate, and a first drain coupled to the current supply. A second CMOS tr... | 04/02/2002 |
| 6366140 | High bandwidth clock buffer A high bandwidth clock buffer, including a steering circuit, significantly increases the maximum frequency at which CMOS technology can be used to perform high-speed logic functions. In particular, the clock buffer includes a steering circuit for enhancin... | 04/02/2002 |
| 6366226 | System for quantizing an analog signal utilizing a resonant tunneling diode differential ternary quantizer A system for quantizing an analog signal comprises an input terminal for receiving an analog input signal, an inverted input terminal for receiving an inverted input signal, a clock terminal for receiving a clock signal, and an inverted clock terminal for... | 04/02/2002 |
| 6359497 | Automatic lockup low-voltage biasing circuit Presented is a low-voltage automatic lock-up biasing circuit with input terminals that accept input voltages, and with an internal node coupled to both input terminals an which takes take the highest of the voltage values applied to the input terminals. T... | 03/19/2002 |
| 6353343 | ISI-rejecting differential receiver A digital differential receiver IC that rejects the inter-symbol interference (ISI) that is imposed upon differential digital signals when long runs of a digital state (0 or 1) are transmitted over long cables. The ISI-rejecting differential receiver IC i... | 03/05/2002 |
| 6344762 | Bias circuit for a low voltage differential circuit A bias circuit that provides biasing for a differential circuit. The bias circuitincludes first and second transistors, first and second impedance devices, a reference current source and an amplifier. The first and second transistors each have a control i... | 02/05/2002 |
| 6342805 | System and method for selectively connecting one of at least two outputs of an associated circuit to an output node A system and method for selecting an output of an associated circuit includes a pair of inputs for receiving different relative voltage levels. A first switch is operatively coupled to a first of the inputs and a second switch operatively coupled to a sec... | 01/29/2002 |
| 6339355 | Offsetting comparator device and comparator circuit An offsetting comparator device includes master and slave comparator circuits and a reference differential voltage generator. The master comparator circuit supplies a sensed current corresponding to a potential difference represented by a differential sig... | 01/15/2002 |
| 6333672 | Differential logic circuit and method of use A differential logic gate (36) is provided with three current sources (56, 58and 60). Current source (56) provides keep alive current flowing through transistor (48) when a logic low is presented at the base terminal of transistor 48. Current source (60) ... | 12/25/2001 |
| 6326815 | Sense amplifier of semiconductor integrated circuit A semiconductor integrated circuit includes a sense amplifier for amplifying an input signal and an complementary input signal, a full differential amplifier for amplifying the output of the sense amplifier, and a latch for latching the output of the full... | 12/04/2001 |
| 6323699 | Method and apparatus for variably providing an input signal A method for variably providing an input signal includes receiving a set of complementary signals and a set of control signals. The method further includes outputting a selected one of a single-ended and a differential signal using at least one of the rec... | 11/27/2001 |
| 6320425 | Dual FET differential voltage controlled attenuator A dual FET differential voltage controlled attenuator includes a first voltage controlled FET transistor (M1), corresponding to a first control voltage terminal, and a second voltage controlled FET transistor (M2), corresponding to a second control voltag... | 11/20/2001 |
| 6320426 | Self-calibrating circuit of high speed comparator A self-calibrating circuit of a high speed comparator, having a first negative phase logic switch, a second negative logic switch, a first positive phase logic switch, a second positive phase logic switch, a third negative phase logic switch, a fourth neg... | 11/20/2001 |
| 6313667 | Apparatus and method for a turn around stage having reduced power consumption, Class AB behavior, low noise and low offset The invention includes a differential input stage that is coupled to a turn around stage with a differential output. The input common mode voltage range is independent of the output common mode voltage range and the electronic circuitry is suited for use ... | 11/06/2001 |
| 6310571 | Multiplexed multi-channel bit serial analog-to-digital converter A circuit includes an analog-to-digital (A/D) converter for multiplexing between a number of analog input signals and converting the selected analog input signals to a digital code representation. The A/D converter includes a comparator having a first inp... | 10/30/2001 |
| 6304107 | Comparator metastability performance from an enhanced comparator detection circuit A detection circuit for receiving a pair of unstable input signals along a pair of input leads and providing a stable output signal along an output lead, preferably to downstream circuitry. The detection circuit includes a plurality of transistors includi... | 10/16/2001 |
| 6300804 | Differential comparator with dispersion reduction circuitry A differential comparator is disclosed including first and second input amplifier circuits. The input amplifier circuits have respective signal input terminals for receiving respective first and second complementary input signals and respective output ter... | 10/09/2001 |
| 6294949 | Voltage drive circuit, voltage drive apparatus and semiconductor-device testing apparatus A circuit includes a first current path formed by a resistance R2, a transistor Q2, a transistor Q5 and a resistance R5. When an input signal A is low, a current i4 flows through the first circuit and the circuit outputs a shift voltage shifted from a con... | 09/25/2001 |
| 6292032 | High impedance circuit A high impedance circuit capable of operating at a low voltage without narrowing the dynamic range is provided, which includes a first and a second transistors forming differential-pair type circuit, a third and fourth transistors, a pair of collector res... | 09/18/2001 |
| 6292028 | Output circuit for a transmission system An output circuit for a transmission system is disclosed. The output circuit of the present invention comprises an input terminal receiving an input logical signal, a first output terminal outputting a first output logical signal having a logic correspond... | 09/18/2001 |
| 6288577 | Active fail-safe detect circuit for differential receiver A fail-safe circuit for a differential receiver can tolerate high common-mode voltages. An output from a differential amplifier that receives a V+ and a V- differential signal can be blocked by a NOR gate when the fail-safe condition is detected, such as ... | 09/11/2001 |
| 6288576 | Fast pre-amplifier for an interface arrangement An interface arrangement including the cascade connection of a differential pre-amplifier (HPA1, HPA2) and a comparator (DA), and generally known as fast Low Voltage Differential Signal [LVDS] circuit for interfacing electronic chips. The current standard... | 09/11/2001 |
| 6281715 | Low voltage differential signaling driver with pre-emphasis circuit A low voltage differential signaling ("LVDS") line driver includes a pre-emphasis circuit to increase the drive capability of the LVDS line driver. A current source provides a first drive current to a current steering circuit. The pre-emphasis circuit inc... | 08/28/2001 |
| 6278299 | Voltage to current converter A voltage to current converter comprises a first long tail pair comprising transistors whose emitters are connected via equal value resistors to a constant current source. The first long tail pair forms a main transconductance stage. A subsidiary or corre... | 08/21/2001 |
