Celebrity Inventors
Comic actor Danny Kaye received patent D166,807 for the co-design of "Blowout Toy or the Like". It's similar to one of those toys that unravels when you blow into at a birthday party except Kaye's has three blowouts going in different directions, not just one.
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| Number | Title | Issue Date |
| 8179162 | Phase-lock assistant circuitry Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured... | 05/15/2012 |
| 7855580 | Phase comparator, phase synchronizing circuit, and phase-comparison control method A phase comparator includes an edge detecting unit to which a reference signal is input and to which a referred signal based on the reference signal is input as a feedback signal. The edge detecting unit detects an edge of the reference signal and an edge of the ref... | 12/21/2010 |
| 7683675 | Radiation hardened phase frequency detector for implementing enhanced radiation immunity performance A method and radiation hardened phase frequency detector (PFD) are provided for implementing enhanced radiation immunity performance. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes dupl... | 03/23/2010 |
| 7629816 | Method and apparatus for pre-clocking A method and apparatus for pre-clocking have been disclosed. In one case pre-clocking is used to effectively decrease the delay to output timing with respect to a clock. In another case pre-clocking is used to allow an output signal more time to reach a given level.... | 12/08/2009 |
| 7482842 | Radiation hardened phase frequency detector for implementing enhanced radiation immunity performance A radiation hardened phase frequency detector (PFD) is provided for implementing enhanced radiation immunity performance. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated compo... | 01/27/2009 |
| 7443251 | Digital phase and frequency detector Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a p... | 10/28/2008 |
| 7375557 | Phase-locked loop and method thereof and a phase-frequency detector and method thereof The phase-frequency detector may include a first flip-flop configured to generate a first signal, the first signal transitioning to a first logic level in response to a first edge of a first input signal and transitioning to a second logic level in response to a del... | 05/20/2008 |
| 7375558 | Method and apparatus for pre-clocking A method and apparatus for pre-clocking have been disclosed. ... | 05/20/2008 |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7355458 | Output driver circuit and a method of transmitting an electrical signal via an output driver circuit In an output driver circuit, the signal propagation time of an electrical signal which is to be transmitted between two selected driver stages is ascertained. If the ascertained signal propagation time is at least equal to half the period duration of the signal whic... | 04/08/2008 |
| 7355387 | System and method for testing integrated circuit timing margins An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit includes circuitry for testing the timing margins of memory devices by determining the re... | 04/08/2008 |
| 7336106 | Phase detector and method having hysteresis characteristics A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the feedback clock signal lags the reference clock signal by more than a seco... | 02/26/2008 |
| 7328381 | Testing system and method for memory modules having a memory hub architecture A testing method and system is used to test memory modules each of which has a memory hub coupled to a plurality of memory devices. The testing system and method includes a test interface circuit having a memory interface that is coupled to transmit and receive memo... | 02/05/2008 |
| 7319340 | Integrated circuit load board and method having on-board test circuit An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit generates test signals that are applied to the integrated circuit sockets. The integrated... | 01/15/2008 |
| 7319350 | Lock-detection circuit and PLL circuit using same A lock-detection circuit that can set an acceptable phase-error range adapted to define a locked state and/or an unlocked state at a constant rate without being affected by a frequency and that can detect the locked state and/or the unlocked state with precision wit... | 01/15/2008 |
| 7304510 | Digital phase detector improving phase detection resolution thereof A digital phase detector has a plurality of first delay elements through which a first clock is delayed, a plurality of second delay elements through which a second clock is delayed, and a plurality of data holding circuits. The data holding circuits latch the first... | 12/04/2007 |
| 7288997 | Phase lock loop and the control method thereof A phase lock loop and the control method thereof. The phase lock loop adjusts operating states automatically to generate a feedback clock for tracing a reference clock. The control method generates the first and second clocks corresponding to the highest and lowest ... | 10/30/2007 |
| 7268630 | Phase-locked loop using continuously auto-tuned inductor-capacitor voltage controlled oscillator Improved voltage controlled oscillator circuits and phase-locked loop circuits are disclosed. For example, a voltage controlled oscillator circuit comprises a first linear amplifier, the first linear amplifier generating a coarse-tuning voltage from an input voltage... | 09/11/2007 |
| 7250798 | Synchronous clock generator including duty cycle correction A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer... | 07/31/2007 |
| 7234070 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 06/19/2007 |
| 7218158 | Self-timed fine tuning control A device and system having improved timing control of input signals. Specifically, a fine delay block is provided having feedback loops therein such that the fine delay block is self tuning. The output of the fine delay block may be implemented to control a coarse d... | 05/15/2007 |
| 7212053 | Measure-initialized delay locked loop with live measurement A method of operating a delay locked loop is comprised of producing a first output signal in response to a first lock point. A new lock point is measured, or otherwise determined, while continuing to produce the first output signal. Thereafter, a second output signa... | 05/01/2007 |
| 7208989 | Synchronous clock generator including duty cycle correction A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer... | 04/24/2007 |
| 7205851 | Semiconductor integrated circuit having a clock generation circuit During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a r... | 04/17/2007 |
| 7161391 | Skew tolerant high-speed digital phase detector A skew-tolerant digital phase detector is provided. Specifically, a detector is provided in the digital phase detector to detect certain failure conditions that may result from clock skew and duty cycle distortion. If the condition is detected, an adjusted signal is... | 01/09/2007 |
| 7159092 | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to store the signals responsive to the clock. A phase command for each digit... | 01/02/2007 |
| 7145367 | Fractional-integer phase-locked loop system with a fractional-frequency-interval phase frequency detector A phase-locked loop circuit has a fractional-frequency-interval phase frequency detector, a charge pump, an oscillator, and a divider. The fractional-frequency-interval phase frequency detector has a phase frequency detector unit that is utilized as or comprises a p... | 12/05/2006 |
| 7137024 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 11/14/2006 |
| 7119583 | Phase detector and method having hysteresis characteristics A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the feedback clock signal lags the reference clock signal by more than a seco... | 10/10/2006 |
| 7116143 | Synchronous clock generator including duty cycle correction A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer... | 10/03/2006 |
| 7106632 | Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells (416) capable of multilevel or analog voltage l... | 09/12/2006 |
| 7088274 | Difference amplifier for digital-to-analog converter An improved circuit is provided that buffers the output of a DAC while improving the bandwidth and linearity of the circuit. A DAC comprises an output signal of a switched DAC circuit coupled to an inverting node of an output buffer configured as a difference amplif... | 08/08/2006 |
| 7084670 | Phase-frequency detector with gated reference clock input A gated phase-frequency detector circuit includes a phase-frequency detector and a multiplexer circuit. The phase-frequency detector is arranged to provide UP and DOWN signals responsive to a reference clock signal and a feedback signal. Further, the phase-frequency... | 08/01/2006 |
| 7085975 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 08/01/2006 |
| 7049852 | Fractional-integer phase-locked loop system with a fractional-frequency-interval phase frequency detector A phase-locked loop circuit has a fractional-frequency-interval phase frequency detector, a charge pump, an oscillator, and a divider. The fractional-frequency-interval phase frequency detector has a phase frequency detector unit that is utilized as or comprises a p... | 05/23/2006 |
| 7046530 | Method and apparatus for current limiting of an output of a DC-to-DC converter A method for current limiting of an output of a DC-to-DC converter begins by determining a current loading duty cycle of the output of the DC-to-DC converter (i.e., the present duty cycle given the loading of on the output). The processing then continues by comparin... | 05/16/2006 |
| 7042970 | Phase frequency detector with adjustable offset A phase detection apparatus is described for use in a phase lock loop (PLL). The apparatus has a first input for a reference signal, a second input for a loop feedback signal and an output for the phase difference signal. Two D-type flips flops are provided, the fir... | 05/09/2006 |
| 7038496 | Device for comparison of frequencies with low temporal inertia The present invention relates to a device for comparison CMP, which is designed to emit a control signal Vcnt, which is representative of a difference which exists between the input signal frequencies Vdiv and Vref. The device according to the invention includes a p... | 05/02/2006 |
| 7016451 | Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ... | 03/21/2006 |
| 7009461 | Phase shifted binary transmission encoder, a phase modulator, and an optical network element for encoding phase shifted binary transmission The invention relates to a phase shifted binary transmission encoder with data input and data output, where the phase shifted binary transmission encoder includes an exclusive or gate having two inputs and one output, the output of the exclusive or gate being the ou... | 03/07/2006 |
