Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
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| Number | Title | Issue Date |
| 8154321 | Method and apparatus for time-differential comparison of an analog signal A time-differential analog comparator is disclosed. An example apparatus according to aspects of the present invention includes a source of a variable frequency signal having a frequency responsive to an analog input. A counting circuit is coupled to count cycles of... | 04/10/2012 |
| 7750685 | Frequency measurement based frequency locked loop synthesizer A first embodiment of the present invention relates to a frequency and phase locked loop (FPLL) synthesizer having a frequency-locked loop (FLL) operating mode and a phase-locked loop (PLL) operating mode. The FLL operating mode is used for rapid coarse tuning of th... | 07/06/2010 |
| 7532040 | Programmable sensitivity frequency coincidence detection circuit and method A frequency coincidence detection circuit for detecting frequency edges for each of a plurality of periodic digital signals. The circuit generates count indicators for each of the periodic digital signals and compares each of the count indicators to a programmable s... | 05/12/2009 |
| 7352214 | System and method for clock detection with glitch rejection A system and a method are presented for detecting the presence of at least one clock signal of a defined clock frequency applied to at least one input port of an integrated circuit system, wherein the a first number M of clock pulses related to the at least one cloc... | 04/01/2008 |
| 7343510 | Method and device for selecting one of multiple clock signals based on frequency differences of such clock signals A clock detection and selection circuit (100) can include a first counter (102-0) that generates a first count value CNT1 according to a first clock signal CLK1 and a second counter (102-1) that generates a second cou... | 03/11/2008 |
| 7343512 | Controlling clock rates of an integrated circuit including generating a clock rate control parameter from integrated circuit configuration Systems and methods for controlling clock rates of circuits are provided. The systems and methods, collectively referred to as clock rate control, generate a clock rate control parameter from data of one or more fuses. The clock rate control detects any overclocked ... | 03/11/2008 |
| 7292070 | Programmable PPM detector A device such as a programmable logic device (“PLD”) includes circuitry for detecting the PPM frequency difference between two input clock signals. For example, this circuitry may accept a user-programmable PPM threshold value and output a signal when this thres... | 11/06/2007 |
| 7279945 | High resolution phase locked loop A phase locked loop (PLL) generates a phase locked signal and adjusts a frequency of the phase locked signal according to an incoming signal. The PLL includes an oscillator for generating the phased locked signal and a frequency detection module electrically coupled... | 10/09/2007 |
| 7242223 | Clock frequency monitor A frequency monitor circuit (FMC) that is part of an integrated circuit chip for monitoring the frequency of one or more clocks present on the chip is disclosed. The FMC includes a reference window generator, operative to output a reference window signal of a given ... | 07/10/2007 |
| 7224751 | Device and method for checking whether a signal with a predetermined frequency is being received A device and method are disclosed, whereby the normally complicated and difficult frequency determination is achieved by simply arranged and executed measures, namely by means of larger, smaller and/or equal comparisons and a counting of certain events. The inventio... | 05/29/2007 |
| 7222254 | System and method for over-clocking detection of a processor utilizing a feedback clock rate setting A processor provides a configured clock rate setting for use by a peripheral set. The processor receives back from the peripheral set a feedback clock rate setting. The configured clock rate setting and the feedback clock rate setting are compared to detect over-clo... | 05/22/2007 |
| 7215133 | Contactless circuit testing for adaptive wafer processing A system and method for measuring circuits on an integrated circuit substrate includes a measurement circuit formed on the integrated circuit substrate that measures at least one characteristic of an integrated circuit. The measurement circuit has a power transfer d... | 05/08/2007 |
| 7154305 | Periodic electrical signal frequency monitoring systems and methods Systems and methods for monitoring frequencies of periodic electrical signals are disclosed. According to one technique, a first and second counters are respectively clocked by a first periodic electrical signal to be monitored and a second periodic electrical, and ... | 12/26/2006 |
| 7148755 | System and method to adjust voltage A system and method that can be utilized to implement voltage adjustment (e.g., for an integrated circuit). In one embodiment, the system comprises a frequency generator that provides a clock signal having a frequency that varies based on an operating voltage. The s... | 12/12/2006 |
| 7136320 | Method and regulating circuit for refreshing dynamic memory cells A method and circuit for refreshing dynamic memory cells arranged along word lines and bit lines are provided, the memory cells being refreshed in a manner dependent on a refresh signal with a refresh frequency by the activation of the word line in order to write th... | 11/14/2006 |
| 7134037 | Method and apparatus for limiting processor clock frequency A method and apparatus for limiting a processor clock frequency includes an overclocking prevention circuit. The overclocking prevention circuit includes a frequency limiting circuit having programmable fusible elements. The frequency limiting circuit outputs a sign... | 11/07/2006 |
| 7116101 | Specific location of hall chips for sensing redundant angular positions A Hall-effect sensor apparatus, system and method. In general, a substrate having a surface can be provided. A plurality of Hall-effect sensing elements can then be configured upon the substrate, such that the centerline of a sensing plane associated with the plural... | 10/03/2006 |
| 7095353 | Frequency to digital conversion A technique of processing an input signal having an input signal phase is disclosed. The technique includes determining a number of transitions of the input signal within a period having a start and an end. The technique includes determining a relative beginning pha... | 08/22/2006 |
| 7095254 | Method for producing a control signal which indicates a frequency error A method which provides a very simple way of forming a control signal if the frequencies differ too greatly from one another between a useful signal and a reference signal. A control signal is produced which indicates that the frequency error between the frequencies... | 08/22/2006 |
| 7089441 | Clock multiplier selection for a microprocessor with multiple system bus clocking frequencies Clock multiplier selection methods and apparatuses. One embodiment includes a clock interface to receive a clock signal, a frequency detect circuit, and a multiplier selection circuit. The frequency detect circuit detects an operating frequency of the clock signal a... | 08/08/2006 |
| 7076084 | Methods and objects employing machine readable data A tangible object (such as a microprocessor, wristwatch, pharmaceutical, compact disc, vehicle part, etc) is surface-textured to encode a plural-bit code thereon. In one arrangement, this encoding conveys date information. In use, the object can be imaged by a scann... | 07/11/2006 |
| 7057427 | Power on reset circuit A power on reset (POR) circuit for providing a reset pulse signal to a chip when power supply voltage, VDD, ramps up so that the chip always starts in a known state. The POR circuit generates the reset pulse as soon as VDD exceeds an assertion voltage. The assertion... | 06/06/2006 |
| 7046964 | Method and apparatus for determining the frequency of a radio signal during periods of stability and monitoring communications with a radio receiver A method and apparatus provide for monitoring radio frequency signals and, in conjunction with the monitoring, determining frequency of a received dominant radio frequency signal. Zero amplitude transitions of the signal are counted in primary and secondary sampling... | 05/16/2006 |
| 6967477 | Adaptive geartooth sensor with dual peak detectors and true power on capability Methods and systems for detecting a rotating target are disclosed herein, wherein a biasing magnet is associated with a rotating target in association with a dual peak detector. The rotating target generally comprises a plurality of teeth and at least one slot forme... | 11/22/2005 |
| 6949959 | Method for converting electric signals and a converter therefor The invention relates to signal conversion devices to be used for the receiving radio devices. The attained technical result is the detection and conversion of signals in an electrical two-terminal device, a data loss level being minimal. A converting element is sup... | 09/27/2005 |
| 6891404 | Auto-adjustment of self-refresh frequency A method of adjusting a control signal that includes generating a control signal at an unknown frequency and automatically adjusting the unknown frequency of the control signal based on the unknown frequency. ... | 05/10/2005 |
| 6891402 | Clock's out-of-synchronism state detection circuit and optical receiving device using the same A detection circuit which can reliably detect an out-of-synchronism state of a clock signal with respect to data even if jitter is present in a data signal. A delayed clock signal obtained by delaying a clock signal by 90° through a delay circuit is input to a data... | 05/10/2005 |
| 6834093 | Frequency comparator circuit A frequency comparator circuit is configured to compare whether the frequency of two input signals are within a tolerance of each other. The frequency comparator circuit includes two counter circuits, an AND gate, and a frequency detector circuit that is configured ... | 12/21/2004 |
| 6807225 | Circuit and method for self trimming frequency acquisition A circuit and method is disclosed for self trimming in frequency acquisition and clock recovery. The circuit can be simplified as having a VCO in communication with three loops including a trimming loop, a frequency loop and a phase loop. The trimming loop includes ... | 10/19/2004 |
| 6788044 | Frequency change measuring device A frequency change measuring device includes frequency divider for frequency dividing a measuring signal to produce frequency-divided signals, first counter for counting the frequency-divides signals to calculate frequency-division numbers, frequency division number... | 09/07/2004 |
| 6771063 | Methods and systems for improving the duty cycle output of a vehicle speed sensor circuit A system for improving the duty cycle output of a vehicle speed sensor circuit is disclosed. The vehicle speed sensor circuit can be configured, for example as a binary counter, to provide a particular number of pulses per distance of vehicle travel. An output of th... | 08/03/2004 |
| 6750682 | Method of and apparatus for detecting difference between frequencies, and phase locked loop circuit An apparatus for detecting a difference between frequencies includes a beat waveform generator which generates a beat waveform signal having a frequency which is equal to a difference between frequencies of a reference clock signal and a target clock signal. A frequ... | 06/15/2004 |
| 6731139 | Short circuit protection apparatus with self-clocking self-clearing latch A latch for detecting a state transition of an input signal and generating a self-clearing reset signal on an output. The latch comprises: 1) a transfer gate for passing the input signal to a first node when the input transfer gate is enabled; 2) a transition detect... | 05/04/2004 |
| 6661266 | All digital built-in self-test circuit for phase-locked loops In general, a built-in self test circuit and method is provided that measures error in any periodic signal and, particularly, a Phase Lock Loop (PLL) output clock signal. The circuit includes a short-pulse generator that generates a short-pulse signal hav... | 12/09/2003 |
| 6597205 | High accuracy method for determining the frequency of a pulse input signal over a wide frequency range A method and system for determining the frequency of a pulse input signal is disclosed. A pulse count and a timer count can be captured at a start and end of a predetermined measurement interval to thereby obtain a start pulse count and an end pulse count... | 07/22/2003 |
| 6563346 | Phase independent frequency comparator A method and circuit for comparing the frequencies of two clocks (clock-- 1 and clock-- 2), without taking into account their phase, is disclosed. Each clock is associated to a circular counter (100-1 and 100-2) which are initialized... | 05/13/2003 |
| 6501310 | Sampling clock adjusting method, and an interface circuit for displaying digital image The PLL (Phase Lock Loop) circuit generates a sampling clock for sampling an analog image signal and a second clock having a frequency equal to that of the sampling clock and a phase different from that of the sampling clock based on the horizontal synchr... | 12/31/2002 |
| 6362693 | Frequency detection method for adjusting a clock signal frequency and a frequency detector circuit for carrying out the method In a frequency detection method for adjusting a clock signal frequency to the data rate of a received data signal, the clock signal which is predivided by a factor of 4. The predivided clock signal and the received data signal are each frequency-divided b... | 03/26/2002 |
| 6331792 | Circuit and method for unlimited range frequency acquisition An improved frequency detector circuit and method is disclosed for frequency acquisition. The frequency detector is particularly useful as part of a frequency loop in a standard two loop clock and data recovery (CDR) circuit because, for among other reaso... | 12/18/2001 |
| 6326826 | Wide frequency-range delay-locked loop circuit A delay-locked loop (DLL), including frequency detection logic and a phase detector, is described having an operating range as wide as a conventional charge pump phase locked loop. The frequency detector logic counts the number of rising edges of the mult... | 12/04/2001 |
