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| Number | Title | Issue Date |
| 7847597 | Precision frequency change detector A frequency change detector splits a frequency standard signal into two undelayed frequency signals, one of which is delayed by a predetermined amount. The delayed signal is then mixed with the undelayed frequency signal into a mixed signal that is further filtered ... | 12/07/2010 |
| 7821302 | Frequency monitor A method and system for monitoring a frequency of a clock signal is disclosed. The method and system comprise dividing a clock signal into a plurality of clock signal components. The method and system further comprise adding a delay to each of the clock signal compo... | 10/26/2010 |
| 7764088 | Frequency detection circuit and detection method for clock data recovery circuit A frequency detection circuit and a detection method thereof suitable for a clock data recovery (CDR) circuit are provided. The frequency detection circuit includes a phase detector, a first delayer, a frequency detector, and a logic circuit. The phase detector samp... | 07/27/2010 |
| 7750684 | Power-on detection circuit for detecting minimum operational frequency A power-on detection circuit for detecting a minimum operational frequency includes: an oscillating circuit, which includes: a ring oscillator, for generating a first oscillating signal; and a high pass filter for filtering the first oscillating signal to generate a... | 07/06/2010 |
| 7737730 | Method of detecting the frequency of an input clock signal of an integrated circuit and integrated circuit An integrated circuit includes a first switched capacitor element and a second switched capacitor element, which are coupled to form a bridge circuit, the first switched capacitor element being located in a first branch of the bridge circuit and the second switched ... | 06/15/2010 |
| 7504865 | Frequency sensor and semiconductor device A frequency sensor includes at least one a resistor element and a capacitor. A frequency is detected according to a charging/discharging time to/from the capacitor, thereby realizing a frequency sensor with reduced power consumption and reduced circuit scale. Furthe... | 03/17/2009 |
| 7471117 | Circuit for detecting maximal frequency of pulse frequency modulation and method thereof The circuit for detecting the maximal frequency of the pulse frequency modulation includes an oscillator-controlling unit, a delay circuit and a master-slave register. The oscillator-controlling unit is connected to an oscillator, which generates the pulse frequency... | 12/30/2008 |
| 7427879 | Frequency detector utilizing pulse generator, and method thereof The present invention discloses a frequency detecting apparatus for detecting a frequency of an input clock. The frequency detecting apparatus includes: a pulse generator, a digital signal generator, and a decoder. The pulse generator is coupled to the input clock f... | 09/23/2008 |
| 7401306 | Apparatus and method for verification support, and computer product A verification support apparatus verifies an object. The object includes a plurality of clock domains and each clock domain includes a plurality of registers. The verification support apparatus includes an input receiving unit that receives logical circuit descripti... | 07/15/2008 |
| 7372312 | Pulse width modulation generating circuit A pulse width modulation (PWM) generating circuit includes a first comparator, a first resistor, a second resistor, a third resistor, a fourth resistor, a capacitor, and a diode. The first resistor and the second resistor are connected in series between a voltage in... | 05/13/2008 |
| 7368955 | Current-balanced logic circuit In accordance with some embodiments, a current-balanced logic circuit includes a first sense amplifier, a second sense amplifier, and a current-source transistor which provides bias current to the first and second sense amplifiers. The first and second sense amplifi... | 05/06/2008 |
| 7356106 | Clock and data recovery circuit A clock and data recovery (CDR) circuit comprises a phase detector (PD) and a quadrature phase (QP) detector. A frequency detector (FD) is coupled to the PD and QP detector. The FD detects frequency difference between the output signals of the PD and QP detector and... | 04/08/2008 |
| 7343512 | Controlling clock rates of an integrated circuit including generating a clock rate control parameter from integrated circuit configuration Systems and methods for controlling clock rates of circuits are provided. The systems and methods, collectively referred to as clock rate control, generate a clock rate control parameter from data of one or more fuses. The clock rate control detects any overclocked ... | 03/11/2008 |
| 7310396 | Asynchronous FIFO buffer for synchronizing data transfers between clock domains An asynchronous FIFO buffer communicates data between first and second clock domains. The FIFO buffer includes a shift register that accepts and shifts out data at a relatively high output frequency required for the second clock domain. The input data is loaded into... | 12/18/2007 |
| 7292070 | Programmable PPM detector A device such as a programmable logic device (“PLD”) includes circuitry for detecting the PPM frequency difference between two input clock signals. For example, this circuitry may accept a user-programmable PPM threshold value and output a signal when this thres... | 11/06/2007 |
| 7279945 | High resolution phase locked loop A phase locked loop (PLL) generates a phase locked signal and adjusts a frequency of the phase locked signal according to an incoming signal. The PLL includes an oscillator for generating the phased locked signal and a frequency detection module electrically coupled... | 10/09/2007 |
| 7259595 | Circuit and method for detecting frequency of clock signal and latency signal generation circuit of semiconductor memory device with the circuit A frequency detection circuit and method of detecting the frequency of a clock signal, and a latency signal generation circuit for a semiconductor memory device that includes the frequency detection circuit. The frequency detection circuit includes a frequency detec... | 08/21/2007 |
| 7242223 | Clock frequency monitor A frequency monitor circuit (FMC) that is part of an integrated circuit chip for monitoring the frequency of one or more clocks present on the chip is disclosed. The FMC includes a reference window generator, operative to output a reference window signal of a given ... | 07/10/2007 |
| 7242216 | Embedding memory between tile arrangement of a configurable IC Some embodiments of the invention provide a configurable IC that includes several configurable computational tiles and several memory tiles. These tiles are arranged in a particular tile arrangement. Each computational tile has a set of configurable logic circuits f... | 07/10/2007 |
| 7236894 | Circuits, systems and methods for dynamic reference voltage calibration A circuit, system and method adjusts a reference voltage, such as an internal or external reference voltage VREF, in response to a first voltage at a first contact, such as a pin on a memory controller used for reading or writing data, and a second voltag... | 06/26/2007 |
| 7224751 | Device and method for checking whether a signal with a predetermined frequency is being received A device and method are disclosed, whereby the normally complicated and difficult frequency determination is achieved by simply arranged and executed measures, namely by means of larger, smaller and/or equal comparisons and a counting of certain events. The inventio... | 05/29/2007 |
| 7215163 | Method and device for frequency division and demultiplexing A device and method is described for the frequency division of an input clock signal, in which from the input clock signal at least two output clock signals are generated, with an output pulse frequency equal to an input pulse frequency divided by a given factor, wh... | 05/08/2007 |
| 7216279 | Testing with high speed pulse generator An integrated circuit, where a hard macro is resident within the integrated circuit. The hard macro receives a clock signal at a frequency that is below the operational frequency of the integrated circuit, and produces a clock signal having a frequency that is at le... | 05/08/2007 |
| 7203254 | Method and system for synchronizing in a frequency shift keying receiver The invention provides a method and apparatus for achieving timing synchronization during signal acquisition and for achieving frequency synchronization in a digital communication receiver after signal acquisition. The invention operates by performing multiple corre... | 04/10/2007 |
| 7183810 | Circuit and method for detecting phase A circuit for detecting phase includes a first inverter, a second inverter, a differential amplifier, an output load latch and an output latch. The first and second inverters receive an input signal and an inverted input signal to generate first and second different... | 02/27/2007 |
| 7171323 | Integrated circuit having clock trim circuitry An integrated circuit is provided comprising a processor, an onboard system clock having a ring oscillator for generating a clock signal, a memory, and clock trim circuitry. The processor is arranged to, in response to receiving an external signal, determine the num... | 01/30/2007 |
| 7154305 | Periodic electrical signal frequency monitoring systems and methods Systems and methods for monitoring frequencies of periodic electrical signals are disclosed. According to one technique, a first and second counters are respectively clocked by a first periodic electrical signal to be monitored and a second periodic electrical, and ... | 12/26/2006 |
| 7148755 | System and method to adjust voltage A system and method that can be utilized to implement voltage adjustment (e.g., for an integrated circuit). In one embodiment, the system comprises a frequency generator that provides a clock signal having a frequency that varies based on an operating voltage. The s... | 12/12/2006 |
| 7145367 | Fractional-integer phase-locked loop system with a fractional-frequency-interval phase frequency detector A phase-locked loop circuit has a fractional-frequency-interval phase frequency detector, a charge pump, an oscillator, and a divider. The fractional-frequency-interval phase frequency detector has a phase frequency detector unit that is utilized as or comprises a p... | 12/05/2006 |
| 7134042 | Frequency detection circuit and data processing apparatus A frequency detection circuit according to the present invention has a status holding register for storing rise information and fall information about a check target clock and outputting an error detection signal showing frequency abnormality when information showin... | 11/07/2006 |
| 7116139 | Apparatus and method for controlling operation of a processor device during startup An apparatus for controlling operation of a processor device during startup of the processor device includes: (a) a signal treating circuit receiving a voltage supply signal at a voltage supply locus; the signal treating circuit using the voltage supply signal for g... | 10/03/2006 |
| 7107393 | Systems and method for transferring data asynchronously between clock domains An asynchronous FIFO buffer communicates data between an input clock domain and a relatively slow output clock domain. The input clock frequency is not an even multiple of the output clock frequency, so the data transfer is asynchronous. The FIFO buffer includes a c... | 09/12/2006 |
| 7096137 | Clock trim mechanism for onboard system clock An integrated circuit, comprising a processor, an onboard system clock for generating a clock signal, and clock trim circuitry, the integrated circuit being configured to: (a) receive an external signal; (b) determine either the number of cycles of the clock signal ... | 08/22/2006 |
| 7061287 | Delay locked loop Provided is a delay locked loop comprising: a delay unit for delaying a clock supplied from an external chipset by a predetermined delay amount; a replica for delaying the clock delayed in the delay unit by a delay amount of a clock path and a data path; and a phase... | 06/13/2006 |
| 7053666 | Phase frequency detector Provided is a phase frequency detector for use in a phase locked loop (PLL) or a delay locked loop (DLL), the phase frequency detector including: an UP signal output unit having a first stage operated according to a reference clock delayed by a predetermined time an... | 05/30/2006 |
| 7038496 | Device for comparison of frequencies with low temporal inertia The present invention relates to a device for comparison CMP, which is designed to emit a control signal Vcnt, which is representative of a difference which exists between the input signal frequencies Vdiv and Vref. The device according to the invention includes a p... | 05/02/2006 |
| 7038497 | Differential current mode phase/frequency detector circuit A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be... | 05/02/2006 |
| 7035360 | Device and method for reducing the amplitude of signals A receiver receives a plurality of different signals at the same time. The receiver comprises means for identifying at least one strongest signal of said plurality of different signals and a filter for attenuating said at least one strongest signal with respect to t... | 04/25/2006 |
| 6970688 | Local oscillator signal divider and low-noise converter employing the same A rat race circuit has an annular transmission line formed on a microstrip dielectric substrate. A terminal for port 1 is formed at any given position of the annular transmission line. Respective terminals for port 2 and port 3 are formed at res... | 11/29/2005 |
| 6963735 | Method and arrangement for receiving a frequency modulated signal A method and arrangement for receiving a frequency modulated signal, includes mixing the frequency modulated signal into a low-frequency signal, detecting the falling and rising edges of said low-frequency signal and forming a second signal on the basis of the edge ... | 11/08/2005 |
