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| Number | Title | Issue Date |
| 8138801 | Frequency crossing detection using opposing pattern detectors A system and method are provided for matching a signal (compClk) to a particular frequency band in a multiband communications device. The method accepts a compClk signal, a frequency source is selected from sources collectively covering a range of frequency bands, a... | 03/20/2012 |
| 7956649 | Frequency pattern detector A window sampling system and method are provided for comparing a signal with an unknown frequency to a reference clock. A pattern modulator accepts a compClk signal and supplies a test window with a period equal to n compClk periods, where n is an integer greater th... | 06/07/2011 |
| 7292070 | Programmable PPM detector A device such as a programmable logic device (“PLD”) includes circuitry for detecting the PPM frequency difference between two input clock signals. For example, this circuitry may accept a user-programmable PPM threshold value and output a signal when this thres... | 11/06/2007 |
| 7274185 | Methods of generating internal clock signals from external clock signals and of measuring the frequency of external clock signals and related frequency measuring circuits and semiconductor memory devices Pursuant to certain embodiments of the present invention, methods of generating an internal clock signal in a semiconductor memory device are provided in which the frequency of an external clock signal is measured. A CAS latency value of the semiconductor memory dev... | 09/25/2007 |
| 7242223 | Clock frequency monitor A frequency monitor circuit (FMC) that is part of an integrated circuit chip for monitoring the frequency of one or more clocks present on the chip is disclosed. The FMC includes a reference window generator, operative to output a reference window signal of a given ... | 07/10/2007 |
| 7231009 | Data synchronization across an asynchronous boundary using, for example, multi-phase clocks Additional information on the phase of an external clock signal is obtained by using clock signals to determine if a phase difference between an external clock signal and a first internal sampling clock signal is less than a pre-selected value. If the system determi... | 06/12/2007 |
| 7190192 | High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high freq... | 03/13/2007 |
| 7164377 | Multiplexed voltage reference strategy for codec A shared voltage reference circuit for a codec is shown that includes a voltage reference circuit for producing a reference voltage. A first sample and hold circuit has a first capacitor coupled to an output of the voltage reference circuit through a first switch co... | 01/16/2007 |
| 7148755 | System and method to adjust voltage A system and method that can be utilized to implement voltage adjustment (e.g., for an integrated circuit). In one embodiment, the system comprises a frequency generator that provides a clock signal having a frequency that varies based on an operating voltage. The s... | 12/12/2006 |
| 7109756 | Synchronization of programmable multiplexers and demultiplexers Systems and methods are disclosed to provide clock and data synchronization for input/output interfaces of a programmable logic device. In accordance with one embodiment, a phase-locked loop or a delay-locked loop is employed to synchronize signals for input/output ... | 09/19/2006 |
| 7095254 | Method for producing a control signal which indicates a frequency error A method which provides a very simple way of forming a control signal if the frequencies differ too greatly from one another between a useful signal and a reference signal. A control signal is produced which indicates that the frequency error between the frequencies... | 08/22/2006 |
| 7057422 | Comparator An arrangement and a method in an integrated circuit for tuning and setting a value comprising a comparator circuit having a reference voltage input and a variable voltage input is provided to produce a digital value on an output depending on a comparison between th... | 06/06/2006 |
| 7049852 | Fractional-integer phase-locked loop system with a fractional-frequency-interval phase frequency detector A phase-locked loop circuit has a fractional-frequency-interval phase frequency detector, a charge pump, an oscillator, and a divider. The fractional-frequency-interval phase frequency detector has a phase frequency detector unit that is utilized as or comprises a p... | 05/23/2006 |
| 6950147 | Apparatus and method for discriminating color format An apparatus discriminates a color format. The signal processing paths separate a luminance signal and a color signal from a broadcasting signal based on a plurality of color formats. The direct signal path provides a direct output of the broadcasting signal without... | 09/27/2005 |
| 6949958 | Phase comparator capable of tolerating a non-50% duty-cycle clocks A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and v... | 09/27/2005 |
| 6831485 | Phase frequency detector with a narrow control pulse A phase frequency detector with a narrow control pulse comprises mainly two substantially equivalent phase latches with a narrow control pulse, and a reset signal generating unit. Each phase latch of a narrow control pulse has a clock pulse input end and a signal ou... | 12/14/2004 |
| 6680631 | Setting the speed of clocked circuitry A way is disclosed of establishing at system reset of both physical operating speed limitations imposed on a secondary bus by a circuit layout as well as the speed capabilities of agents attached to the bus, so that a secondary bus clock speed may be set ... | 01/20/2004 |
| 6665367 | Embedded frequency counter with flexible configuration An integrated circuit according to the present invention includes application-specific circuitry and an embedded counter assembly capable of measuring the frequency of one or more clock signals, which may be generated internally by the integrated circuit ... | 12/16/2003 |
| 6642747 | Frequency detector for a phase locked loop system A frequency detector circuit is arranged to detect a frequency difference between a clock signal and a reference clock signal. The frequency detector circuit includes four flip-flop circuits and a clear logic circuit. The clear logic circuit is arranged t... | 11/04/2003 |
| 6636079 | Phase comparing circuit, PLL circuit, televisions broadcasting receiver, and method of comparing phase An object of the present invention is to provide a phase comparing circuit capable of outputting a signal in accordance with phase difference with a high degree of accuracy, even if the phase difference is small. The phase comparing circuit according to t... | 10/21/2003 |
| 6593785 | Method and circuit for reducing power and/or current consumption An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to receive a device input signal. The apparatus may be configured to perform a predefined function in response to the device input signal during normal opera... | 07/15/2003 |
| 6407642 | Frequency detector and phase-locked loop circuit including the detector A three-state phase detector, including two latches and one NAND gate, is provided with two additional latches. To detect a phase difference between first and second input clock signals R and V, the phase detector alternates among three states responsive ... | 06/18/2002 |
| 6392495 | Frequency detector circuits and systems A frequency detector embodying the invention includes circuitry for comparing first (e.g., a reference) and second (e.g., a recovery clock) signals having first and second frequencies, respectively, and for producing an output signal having: (a) a first c... | 05/21/2002 |
| 6362693 | Frequency detection method for adjusting a clock signal frequency and a frequency detector circuit for carrying out the method In a frequency detection method for adjusting a clock signal frequency to the data rate of a received data signal, the clock signal which is predivided by a factor of 4. The predivided clock signal and the received data signal are each frequency-divided b... | 03/26/2002 |
| 6313669 | Buffer circuitry There is provided buffer circuitry that can include a data output circuit for connecting a first power supply to its output terminal when a data applied thereto is at a HIGH level, or connecting a ground to the output terminal when the data is at a LOW le... | 11/06/2001 |
| 6137287 | Physical parameter sensor having a self-testing circuit which recognizes an abnormal sensor state A sensor for detecting a physical parameter is capable of detecting an error state in which normal physical parameter detection is not possible even though the output voltage is within a normal output voltage range is disclosed. Errors such as a normal re... | 10/24/2000 |
| 6081137 | Frequency detecting circuit A frequency detecting circuit is provided that includes a level shift detecting unit for generating pulse signals of a certain pulse width at each level shifting of input clock signals and a level detecting unit. The level detecting unit includes a chargi... | 06/27/2000 |
| 6081143 | Frequency comparison and generation in an integrated processor An integrated processor includes a microprocessor core and a bus interface unit. The integrated processor receives a reference clock signal and an external clock signal. The frequency of the reference clock signal is compared to the frequency of the exter... | 06/27/2000 |
| 6020765 | Frequency difference detector for use with an NRZ signal A frequency difference detector includes a pulse generator that receives an NRZ signal and a reference signal and provides data pulses having first edges based on edges of the NRZ signal and second edges based on edges of the reference signal, a pulse rou... | 02/01/2000 |
| 5959487 | Integrated circuit with speed detector A circuit is designed with a reference circuit (200) for generating a reference signal. The reference signal determines a reference period. A delay circuit (208, 212, 216) responsive to the reference signal produces a delay signal. A control circuit (248,... | 09/28/1999 |
| 5949261 | Method and circuit for reducing power and/or current consumption A semiconductor device (e.g., a zero-delay buffer) is provided which is capable of reducing current or power consumption without the use of a dedicated pin. The device may include a frequency detector that receives a detector input signal corresponding to... | 09/07/1999 |
| 5929670 | Method for improving signal generator frequency precision using counters A method for improving the precision of a signal generator utilizing counters. The difference between an external standard signal frequency and an internal standard frequency is measured by digital counters. The signal of this internal standard frequency ... | 07/27/1999 |
| 5796272 | Frequency deviation detection circuit A frequency departure detecting circuit permits flexibly modify a detecting condition of frequency departure. A working reference clock is counted for a given period. On the basis of uniformity between bits of given number of upper bits of the counted val... | 08/18/1998 |
| 5736873 | Power saving control circuit for a display apparatus A power control circuit of a monitor capable of being applied to all kinds of monitors is constructed to supply a control signal in accordance with the state of the monitor among On, Stand-by, Suspend and Off states by considering the input of vertical an... | 04/07/1998 |
| 5652532 | Frequency difference detection apparatus A frequency difference detection apparatus includes a first PLL, a second PLL, a first phase difference detection unit, a second phase difference detection unit, a phase difference processing unit, and a frequency difference detection unit. The first PLL ... | 07/29/1997 |
| 5650743 | Common mode controlled signal multiplier A common mode controlled signal multiplier includes a pair of interconnected differential amplifiers, each of which receives a common mode signal and an input signal and generates one phase of a differential output signal. In one of the differential ampli... | 07/22/1997 |
| 5619155 | IC-chip operation inhibitor An IC chip operation inhibitor to prevent operation of an IC chip in a system having a clock rate that exceeds a predetermined reference clock rate for the chip. The inhibitor has a frequency detecting device that generates at least one reference frequenc... | 04/08/1997 |
| 5592111 | Clock speed limiter for an integrated circuit A speed governor for an integrated circuit which prevents the operation of the integrated circuit above a selected frequency. The speed governor generates a frequency reference and compares the frequency reference to the frequency of the external clock si... | 01/07/1997 |
| 5592129 | High resolution, large multiplication factor digitally-controlled frequency multiplier A frequency multiplier circuit generates an supplemental high-frequency timing signal from a single, low-frequency current-controlled oscillator (CCO). The current-controlled oscillator (CCO) generates a controlled discharge current and a controlled bias ... | 01/07/1997 |
| 5563928 | Method and apparatus for optimizing the performance of digital systems A free running relaxation oscillator is disposed on a semiconductor integrated circuit die for generating a frequency representative of the natural frequency of the die. The natural frequency of the die changes for different operating temperatures and vol... | 10/08/1996 |
