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...that the first rickshaw was invented in 1869 by an American Baptist minister, the Rev. E. Jonathan Scobie, to transport his invalid wife around the streets of Yokohama?
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| Number | Title | Issue Date |
| 8040158 | Frequency difference detection apparatus and method, frequency discrimination apparatus and method, and frequency synthesis apparatus and method An apparatus having a complex sine wave generating circuit (3) that generates a complex sine wave, a multiplying circuit (4) that multiplies an input signal by the complex sine wave, a first integrating circuit (5) that integrates the product ob... | 10/18/2011 |
| 7373114 | Signal transmission circuit, signal output circuit and termination method of signal transmission circuit This invention provides a signal transmission circuit, a signal output circuit, and a termination method of a signal transmission circuit capable of preventing the re-reflection of the signal at a transmitting node of a transmission path even when an impedance of a ... | 05/13/2008 |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7277093 | Low power apparatus used with a display device A low power apparatus used in a display device, which cuts off unnecessary power to the display device in the event of abnormal inputs of horizontal and/or vertical synchronous signals. The low power apparatus comprises a synchronous signal checking unit to check wh... | 10/02/2007 |
| 7259604 | Initialization scheme for a reduced-frequency, fifty percent duty cycle corrector A reduced-frequency, 50% duty cycle corrector (DCC) circuit may be used in an electronic device (e.g., a memory chip) to generate output clocks with 50% duty cycle irrespective of the duty cycle of the clock input to the DCC circuit. A DCC initialization scheme sele... | 08/21/2007 |
| 7251192 | Register read for volatile memory Data not stored in the DRAM array of a SDRAM module is read from the SDRAM module in a synchronous data transfer. The data transfer, referred to as register read command/operation, resembles a read command/operation directed to data stored in the DRAM array in timin... | 07/31/2007 |
| 7234070 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 06/19/2007 |
| 7230876 | Register read for volatile memory Data not stored in the DRAM array of a SDRAM module is read from the SDRAM module in a synchronous data transfer. The data transfer, referred to as register read command/operation, resembles a read command/operation directed to data stored in the DRAM array in timin... | 06/12/2007 |
| 7231622 | Method for correcting crosstalk In a semiconductor integrated circuit, there is provided a method for correcting crosstalk, which exerts an influence via coupling capacitance between wiring by the signal transitions between adjacent wiring, comprising the step of creating a candidate for buffer di... | 06/12/2007 |
| 7225349 | Power supply voltage droop compensated clock modulation for microprocessors A voltage source droop compensated clock modulation for microprocessors is described. Specifically, the circuit reduces the clock frequency if a voltage source droop is detected. ... | 05/29/2007 |
| 7221613 | Memory with serial input/output terminals for address and data and method therefor A memory (10) has a plurality of memory cells, a transceiver (56) for receiving a low voltage high frequency differential address signal, and a serial input/output data port (52, 54) for receiving a high frequency low voltage differential data s... | 05/22/2007 |
| 7219294 | Early CRC delivery for partial frame Memory apparatus and methods transmit and receive a CRC code for a first portion of a frame before the second portion of the frame is finished being transferred. The CRC may be used to check the first portion of the frame before the second portion of the frame is co... | 05/15/2007 |
| 7190192 | High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high freq... | 03/13/2007 |
| 7159092 | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to store the signals responsive to the clock. A phase command for each digit... | 01/02/2007 |
| 7137024 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 11/14/2006 |
| 7131024 | Multiple transmit data rates in programmable logic device serial interface A serial interface for a programmable logic device provides multiple data rates in different channels by generating a central serial clock and providing at least one divider in each channel that can divide the central clock by different integer values. For additiona... | 10/31/2006 |
| 7126383 | High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high freq... | 10/24/2006 |
| 7085975 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 08/01/2006 |
| 7049852 | Fractional-integer phase-locked loop system with a fractional-frequency-interval phase frequency detector A phase-locked loop circuit has a fractional-frequency-interval phase frequency detector, a charge pump, an oscillator, and a divider. The fractional-frequency-interval phase frequency detector has a phase frequency detector unit that is utilized as or comprises a p... | 05/23/2006 |
| 7030705 | Section selection loop filter and phase locked loop circuit having the same A section selection loop filter for use in a phase lock loop for reducing sizes of hardware and increase ranges of tuning, including a selection signal outputting part for setting a first to fourth sections according to an input tuning voltage, selecting a first to ... | 04/18/2006 |
| 7016451 | Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ... | 03/21/2006 |
| 7009428 | High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high freq... | 03/07/2006 |
| 6998879 | Level determination circuit determining logic level of input signal An input circuit in a DRAM includes a differential amplifier circuit amplifying a potential difference between a potential of an input signal and a reference potential, an inverter outputting an inversion signal of an output signal of the differential amplifier circ... | 02/14/2006 |
| 6959016 | Method and apparatus for adjusting the timing of signals over fine and coarse ranges A variable delay circuit is formed by a fine delay circuit and a coarse delay circuit. The fine delay circuit adjusts the delay of a delayed clock signal in relatively small phase increments with respect to an input clock signal. The coarse delay circuit adjusts the... | 10/25/2005 |
| 6954097 | Method and apparatus for generating a sequence of clock signals A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that ... | 10/11/2005 |
| 6952462 | Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ... | 10/04/2005 |
| 6931086 | Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ... | 08/16/2005 |
| 6927709 | Transmission and reception interface and method of data transmission An N-bit word is produced from an M-bit code received on an M-bit line, M being larger than N, the M-bit code comprising at least an M-bit code word and a previous M-bit code word, the M-bit code word comprising different levels at at least two bit positions, and th... | 08/09/2005 |
| 6891402 | Clock's out-of-synchronism state detection circuit and optical receiving device using the same A detection circuit which can reliably detect an out-of-synchronism state of a clock signal with respect to data even if jitter is present in a data signal. A delayed clock signal obtained by delaying a clock signal by 90° through a delay circuit is input to a data... | 05/10/2005 |
| 6677882 | Multi-octave high-resolution receiver for instantaneous frequency measurements An RF band receiver for concurrently monitoring a plurality of contiguous channels within the RF spectrum to unambiguously detect time-coincident signals. The receiver includes a plurality of transmission paths feeding a like number of digital, mixed-base... | 01/13/2004 |
| 6586971 | Adapting VLSI clocking to short term voltage transients A system and method of compensating for voltage droop in an integrated circuit. The integrated circuit may include a plurality of chip circuits, a clock control system, a clock distribution network including at least one delay element and a voltage droop ... | 07/01/2003 |
| 6360284 | System for protecting output drivers connected to a powered-off load A system for preventing a powered-up sub-unit from driving a powered-off low-impedance load transitions to a NO_CLOCK state and tri-states output drivers of the sub-unit output unless a clock signal is received from a connected sub-unit. While in the NO_C... | 03/19/2002 |
| 6255859 | High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit fo... | 07/03/2001 |
| 6194918 | Phase and frequency detector with high resolution A phase detector for measuring phase differences between K input signals is provided. The phase detector includes a counter, K first registers and a first subtractor. Each first register receives the counter signal of the counter and a respective input si... | 02/27/2001 |
| 6160423 | High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit fo... | 12/12/2000 |
| 5982200 | Costas loop carrier recovery circuit using square-law circuits By using the two square-law circuits for squaring the common mode and orthogonal components of the carrier wave and by using the multiplying circuit for multiplying these squared signals, the Costas loop carrier recovery circuit can be constituted. The ca... | 11/09/1999 |
| 5946362 | Apparatus for detecting clock failure for use in a synchronous transmission system An apparatus for use in a synchronous transmission system, for detecting a failure of a clock signal, which comprises: a reference clock generator for generating a reference clock signal (RCS) in response to a reset signal issued by a system controller in... | 08/31/1999 |
| 5821786 | Semiconductor integrated circuit having function for evaluating AC performance A semiconductor integrated circuit, having circuit blocks to be evaluated in AC performance, includes a first circuit for inputting a first signal and a second signal generated in the interior of the semiconductor integrated circuit. The first circuit out... | 10/13/1998 |
| 5818849 | IC testing apparatus An IC testing apparatus has a detecting circuit for detecting an inversion of an output state of a test output from an IC under test in response to application of a clock signal, a comparing circuit for comparing a value preset in a storage circuit with t... | 10/06/1998 |
| 5796272 | Frequency deviation detection circuit A frequency departure detecting circuit permits flexibly modify a detecting condition of frequency departure. A working reference clock is counted for a given period. On the basis of uniformity between bits of given number of upper bits of the counted val... | 08/18/1998 |
